Semiconductor package including stacked semiconductor chips

1. A semiconductor package comprising:

a substrate including an opening;

a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening;

a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening; and

a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed,

wherein one or more of the second chip pads overlap with the first semiconductor chip and are covered by the first semiconductor chip, with remaining pads of the second chip pads being exposed through the opening, and

wherein the redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads.

2. The semiconductor package of claim 1 , wherein a width of the opening in a first direction is larger than a width of the opening in a second direction substantially perpendicular to the first direction, and

the second semiconductor chip is disposed to partially overlap with the first semiconductor chip in the first direction.

3. The semiconductor package of claim 1 , wherein the substrate has a first surface facing the first semiconductor chip, and a second surface, located opposite to the first surface, and includes first substrate pads, located on the second surface of the substrate.

4. The semiconductor package of claim 3 , further comprising interconnectors configured to connect the first chip pads, the remaining pads of the second chip pads, and the redistribution pads to the first substrate pads through the opening.

5. The semiconductor package of claim 4 , wherein the first substrate pads include one-side first substrate pads, disposed on one side of the opening, and other-side first substrate pads, disposed on the other side of the opening,

wherein the interconnectors, connected to the first chip pads, and the remaining pads of the second chip pads, are connected to the one-side first substrate pads, and

wherein the interconnectors, connected to the redistribution pads, are connected to the other-side first substrate pads.

6. The semiconductor package of claim 1 , wherein the second semiconductor chip is disposed to partially overlap with the first semiconductor chip in the first direction,

the second chip pads are arranged in a line in the first direction, and

the redistribution pads are arranged in a line in the first direction on one side of a row of the second chip pads.

7. The semiconductor package of claim 6 , wherein the substrate has a first surface facing the first semiconductor chip and a second surface located opposite to the first surface and includes one-side first substrate pads located on the second surface of the substrate and disposed on one side of the opening and other-side first substrate pads located on the second surface of the substrate and disposed on the other side of the opening, and

the semiconductor package further comprises:

interconnectors configured to connect the redistribution pads to the one-side first substrate pads and connect the remaining pads of the second chip pads to the other-side first substrate pads.

8. The semiconductor package of claim 1 , wherein the second semiconductor chip is disposed to partially overlap with the first semiconductor chip in the first direction,

the second chip pads include a first row arranged in a line in the first direction and a second row arranged in a line in the first direction on one side of the first row and at least one of the first row and the second row has a space where the second chip pads are not disposed, and

the redistribution pads are disposed in the space.

9. The semiconductor package of claim 8 , wherein the substrate has a first surface facing the first semiconductor chip and a second surface located opposite to the first surface and includes one-side first substrate pads located on the second surface of the substrate and disposed on one side of the opening and other-side first substrate pads located on the second surface of the substrate and disposed on the other side of the opening, and

the semiconductor package further comprises:

interconnectors configured to connect the remaining pads of the second chip pads of the first row or the redistribution pads of the first row to the one-side first substrate pads and connect the remaining pads of the second chip pads of the second row or the redistribution pads of the second row to the other-side first substrate pads.

10. The semiconductor package of claim 1 , wherein the second semiconductor chip is disposed to partially overlap with the first semiconductor chip in the first direction,

the second chip pads include a first row arranged in a line in the first direction and a second row arranged in a line in the first direction on one side of the first row, and

the redistribution pads are arranged in a third row between the first row and the second row in the second direction.

11. The semiconductor package of claim 10 , wherein the redistribution pads are alternately arranged with the second chip pads in the first direction.

12. The semiconductor package of claim 1 , wherein the substrate has a first surface, facing the first semiconductor chip, and a second surface, opposite to the first surface, and includes a power pad located on the second surface of the substrate, and

wherein the redistribution layer further includes an additional redistribution line that connects the second chip pad and the redistribution pad, which are required to be connected to the power pad.

13. The semiconductor package of claim 12 , the semiconductor package further comprising an interconnector configured to connect one of the second chip pad and the redistribution pad, which are required to be connected to the power pad, to the power pad.

14. The semiconductor package of claim 1 , wherein the substrate has a first surface, facing the first semiconductor chip, and a second surface, opposite to the first surface, and includes a ground pad, located on the second surface of the substrate, and

wherein the redistribution layer further includes an additional redistribution line that connects the second chip pad and the redistribution pad, which are required to be connected to the ground pad.

15. The semiconductor package of claim 14 , the semiconductor package further comprising an interconnector configured to connect one of the second chip pad and the redistribution pad, which are required to be connected to the ground pad, to the ground pad.

16. The semiconductor package of claim 1 , wherein the first chip pads are located in a central region of the first semiconductor chip, and

the second chip pads are located in a central region of the second semiconductor chip.

17. The semiconductor package of claim 1 , wherein an arrangement of the first chip pads is substantially equal to an arrangement of the second chip pads.

18. The semiconductor package of claim 2 , wherein both side surfaces of the first semiconductor chip are aligned with both side surfaces of the second semiconductor chip in the second direction.

19. The semiconductor package of claim 3 , wherein the substrate further comprises:

second substrate pads located on the second surface of the substrate and connectable to external connection elements.

20. The semiconductor package of claim 1 , further comprising:

a first adhesive layer located between the first semiconductor chip and the substrate; and

a second adhesive layer located between the redistribution layer and the first semiconductor chip.

21. The semiconductor package of claim 1 , further comprising:

an encapsulant configured to fill the opening while covering the substrate, the first semiconductor chip, and the second semiconductor chip.