System and method for self-invalidation, self-downgrade cachecoherence protocols
Methods and systems for self-invalidating cachelines in a computer system having a plurality of cores are described. A first one of the plurality of cores, requests to load a memory block from a cache memory local to the first one of the plurality of cores, which request results in a cache miss. This results in checking a read-after-write detection structure to determine if a race condition exists for the memory block. If a race condition exists for the memory block, program order is enforced by the first one of the plurality of cores at least between any older loads and any younger loads with respect to the load that detects the prior store in the first one of the plurality of cores that issued the load of the memory block and causing one or more cache lines in the local cache memory to be self-invalidated.
1. A method for self-invalidating cachelines in a computer system having a plurality of cores, the method comprising:
requesting, by a first one of the plurality of cores, to load a memory block from a cache memory local to the first one of the plurality of cores, which request results in a cache miss;
checking a read-after-write detection structure to determine if a race condition exists for the memory block; and
if a race condition exists for the memory block, enforcing program order at least between any older loads and any younger loads with respect to the load that detects a prior store in the first one of the plurality of cores that issued the load of the memory block and causing one or more cache lines in the local cache memory to be self-invalidated.
2. The method of claim 1 , wherein the read-after-write detection structure contains address information associated with stores made by the plurality of cores and wherein the step of checking further comprises:
comparing a target address of the load with the address information in the read-after-write detection structure to determine if the race condition exists.
3. The method of claim 1 , further comprising:
adding, to the read-after-write detection structure, an address associated with an executed store to address information stored in the read-after-write detection structure associated with each of the plurality of cores except for a core which executed the store.
4. The method of claim 1 , wherein checking the read-after-write detection structure comprises accessing a signature table at a level of a shared lower level cache.
5. The method of claim 4 , wherein checking the read-after-write detection structure comprises matching in the signature table a target address of the memory block accessed by the load with a target address of the memory block previously written by one or more stores from one or more other cores.
6. The method of claim 1 , further comprising:
sending, by the first one of the plurality of cores, a request to a shared lower level cache when the cache miss results.
7. The method of claim 1 , wherein the prior store is ordered in the read-after-write detection structure, and wherein the enforcing program order comprises performing the load of the memory block in program order relative to the prior store.
8. The method of claim 1 , wherein the prior store is not ordered, and wherein the enforcing program order comprises delaying performing the load of the memory block.
9. The method of claim 1 , wherein the causing one or more cachelines in the local cache memory to be self-invalidated comprises including an indication that the race condition exists in a response to the load that detects the prior store.
10. The method of claim 9 , wherein the causing one or more cachelines in the local cache memory to be self-invalidated comprises including an identity of a core that executed the prior store.
11. A computer system comprising:
a plurality of cores; and
a read-after-write detection structure,
wherein a first one of the plurality of cores is configured to request to load a memory block from a cache memory local to the first one of the plurality of cores, which request results in a cache miss;
wherein the computer system is configured to check the read-after-write detection structure to determine if a race condition exists for the memory block; and
wherein, if a race condition exists for the memory block, the computer system is configured to enforce program order at least between any older loads and any younger loads with respect to the load that detects a prior store in the first one of the plurality of cores that issued the load of the memory block and cause one or more cache lines in the local cache memory to be self-invalidated.
12. The computer system of claim 11 , wherein the read-after-write detection structure contains address information associated with stores made by the plurality of cores and wherein the computer system is configured to check the read-after-write detection structure to determine if the race condition exists for the memory block by:
comparing a target address of the load with the address information in the read-after-write detection structure to determine if the race condition exists.
13. The computer system of claim 11 , wherein the computer system is configured to add, to the read-after-write detection structure, an address associated with an executed store to address information stored in the read-after-write detection structure associated with each of the plurality of cores except for a core which executed the store.
14. The computer system of claim 11 , wherein the computer system is configured to check the read-after-write detection structure by accessing a signature table at a level of a shared lower level cache.
15. The computer system of claim 14 , wherein the computer system is configured to check the read-after-write detection structure by matching in the signature table a target address of the memory block accessed by the load with a target address of the memory block previously written by one or more stores from one or more other cores.
16. The computer system of claim 11 , wherein the first one of the plurality of cores is configured to send a request to a shared lower level cache when the cache miss results.
17. The computer system of claim 11 , wherein the prior store is ordered in the read-after-write detection structure, and wherein the computer system is configured to enforce program order by performing the load of the memory block in program order relative to the prior store.
18. The computer system of claim 11 , wherein the prior store is not ordered, and wherein the computer system is configured to enforce program order by delaying performing the load of the memory block.
19. The computer system of claim 11 , wherein the computer system is configured to cause one or more cachelines in the local cache memory to be self-invalidated by including an indication that the race condition exists in a response to the load that detects the prior store.
20. The computer system of claim 19 , wherein the computer system is configured to cause one or more cachelines in the local cache memory to be self-invalidated by including an identity of a core that executed the prior store.