Semiconductor fin structures having silicided portions

1. A semiconductor device comprising a fin structure and a substrate, the fin structure comprising:

a first source/drain region;

a second source/drain region; and

a channel region arranged between the first source/drain region and the second source/drain region to separate the first source/drain region and the second source/drain region in a length direction of the fin structure,

wherein the first source/drain region comprises a bottom portion and a top portion, the bottom portion being arranged between the top portion and the substrate such that the bottom portion shares a common boundary with the top portion,

wherein the bottom portion of the first source/drain region is fully silicided, and

wherein the top portion of the first source/drain region is partly silicided.

2. The semiconductor device of claim 1 , wherein the second source/drain region comprises a top portion which is partly silicided.

3. The semiconductor device of claim 2 , further comprising a first connecting structure which electrically contacts at least a part of the bottom portion of the first source/drain region and a second connecting structure which electrically contacts at least a part of the top portion of the second source/drain region.

4. The semiconductor device of claim 3 , wherein the first connecting structure electrically contacts the bottom portion of the first source/drain region from a side of the fin structure facing the substrate and the second connecting structure electrically contacts a surface of the top portion of the second source/drain region from a side of the fin structure facing away from the substrate.

5. The semiconductor device of claim 3 , wherein at least a part of the top portion of the second source/drain region is provided with an epitaxial contacting structure forming part of the second connecting structure.

6. The semiconductor device of claim 1 , wherein the top portion of the first source/drain region comprises a silicided outer layer.

7. The semiconductor device of claim 6 , wherein the top portion of the first source/drain region further comprises an inner portion which has a lower metal concentration than the silicided outer layer.

8. The semiconductor device of claim 1 , wherein the top portion of the first source/drain region fully overlaps the bottom portion of the first source/drain region in a direction transverse to a main plane of extension of the substrate.

9. The semiconductor device of claim 1 , wherein the substrate comprises a well doped with a dopant of a first type, wherein a region of the well sharing a common boundary with the bottom portion of the first source/drain region comprises a higher dopant concentration than other regions of the well, and wherein the top portion of the first and second source/drain regions are doped with a dopant of a second type.

10. A method for forming a semiconductor device, comprising:

forming a fin structure having a first source/drain region, a second source/drain region and a channel region, wherein the channel region is arranged between the first source/drain region and the second source/drain region, thereby separating the first source/drain region and the second source/drain region in a length direction of the fin structure, and wherein the first source/drain region comprises a bottom portion and a top portion, the bottom portion being arranged between the top portion and a substrate of the semiconductor device such that the bottom portion shares a common boundary with the top portion;

depositing a first metal on the top portion of the first source/drain region;

annealing to react the first metal with a material of the top portion of the first source/drain region, such that the top portion of the first source/drain region is partly silicided;

providing a second metal on the bottom portion of the first source/drain region; and

annealing to react the second metal with a material of the bottom portion of the first source/drain region, such that the bottom portion of the first source/drain region is fully silicided.

11. The method of claim 10 , wherein providing the second metal comprises forming a recess exposing sidewalls of the bottom portion of the first source/drain region and depositing the second metal in the recess.

12. The method of claim 10 , further comprising removing the first metal that has not been silicided from portions of the fin structure.

13. The method of claim 10 , further comprising depositing an inter-layer dielectric prior to reacting the second metal.

14. The method of claim 10 , further comprising doping the substrate to form a well such that a region of the well sharing a common boundary with the bottom portion of the first source/drain region comprises a higher dopant concentration than other regions of the well.

15. The method of claim 14 , wherein the doping the substrate comprises forming a recess in the substrate, the recess being positioned adjacent to the fin structure, and at least partly filling the recess with a doped oxide.

16. The method of claim 10 , further comprising doping the bottom portion of the first source/drain region with a solid-phase diffusion process.

17. The method of claim 10 , further comprising:

forming a first connecting structure which electrically contacts at least a part of the bottom portion of the first source/drain region; and

forming a second connecting structure which electrically contacts at least a part of the top portion of the second source/drain region.

18. The method of claim 10 , wherein annealing is such that the top portion of the first source/drain region comprises a silicided outer layer.

19. The method of claim 18 , wherein annealing is such that the top portion of the first source/drain region further comprises an inner portion which has a lower metal concentration than the silicided outer layer.