Display device
A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.
1. A display device, comprising:
a substrate including a display area and a non-display area;
a plurality of pixels in the display area of the substrate;
data lines for supplying a data signal to the pixels and extending in a first direction; and
a first dummy part in the non-display area and adjacent to an outermost pixel located at an outermost side of the display area from among the plurality of pixels,
wherein the first dummy part comprises a first dummy data line and a dummy power pattern extending in parallel to the data lines.
2. The display device of claim 1 , wherein the outermost pixel is connected to an outermost data line of the display area from among the data lines, and
wherein the first dummy part forms a parasitic capacitor with the outermost pixel.
3. The display device of claim 2 , wherein a width of the first dummy part in a second direction crossing the first direction is less than that of each of the pixels.
4. The display device of claim 3 , further comprising scan lines for supplying a scan signal to the pixels, and extending in the second direction,
wherein each of the pixels comprises a transistor, and an organic light emitting element connected to the transistor, the transistor comprising:
an active pattern on the substrate;
source and drain electrodes each connected to the active pattern;
a gate electrode overlapping with the active pattern with a gate insulating layer interposed therebetween; and
an interlayer insulating layer covering the gate electrode, and comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer, which are sequentially stacked.
5. The display device of claim 4 , further comprising a power line for supplying power to the pixels, the power line comprising:
a first power supply line on the second interlayer insulating layer and parallel to the data lines; and
a second power supply line on the third interlayer insulating layer, and comprising first lines parallel to the data lines, and second lines connecting adjacent ones of the first lines to each other.
6. The display device of claim 5 , wherein the dummy power pattern comprises:
a dummy first power line located at a same layer as the first power supply line; and
a dummy second power line located at a same layer as the second power supply line, and electrically connected to the dummy first power line.
7. The display device of claim 6 , wherein the dummy second power line is electrically connected to the second lines of the second power supply line.
8. The display device of claim 6 , wherein each of the pixels further comprises a compensation transistor connected to the gate electrode of the transistor, and configured to be turned on when the scan signal is supplied to a corresponding one of the scan lines to cause the transistor to be diode-connected.
9. The display device of claim 8 , wherein each of the pixels further comprises a shielding pattern on the first interlayer insulating layer, and covering at least a portion of the compensation transistor.
10. The display device of claim 9 , wherein the first dummy part further comprises:
a dummy semiconductor pattern at the same layer as the active pattern, and extending in parallel to the first dummy data line; and
a first dummy shielding pattern on the first interlayer insulating layer, connected to the dummy first power line, and covering at least a portion of the compensation transistor of the outermost pixel.
11. The display device of claim 9 , wherein the display area comprises:
a first display area in which lengths of the scan lines are the same; and
a second display area at at least one side of the first display area, and in which lengths of respective ones of the scan lines decrease as the scan lines become more distant from the first display area.
12. The display device of claim 11 , wherein the first dummy part is in the non-display area corresponding to the first display area.
13. The display device of claim 11 , further comprising a second dummy part in the non-display area adjacent to an outermost pixel of the second display area from among the pixels, and forming a parasitic capacitor with the outermost pixel of the second display area.
14. The display device of claim 13 , wherein the second dummy part comprises a second dummy data line and a second dummy power pattern, which extend in parallel to the data lines.
15. The display device of claim 14 , wherein the second dummy part further comprises a second dummy shielding pattern on the first interlayer insulating layer, and connected to the second dummy power pattern.
16. The display device of claim 15 , wherein the second dummy shielding pattern covers the compensation transistor of the outermost pixel of the second display area.
17. The display device of claim 14 , wherein a width of the second dummy part in the second direction is less than that of each of the pixels.