IP Library Granted Patent US 11,244,920
Granted Patent B2
US 11,244,920 · App. 16/715,532 · Granted Feb 8, 2022

Method and structures for low temperature device bonding

Inventor: Cyprian Emeka Uzoh (San Jose, CA)
Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
H01L24/20H01L24/03H01L24/05H01L24/19H01L24/82H01L25/0657H01L25/50H01L2224/80895
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Quick Facts
Patent No.
US 11,244,920
App. No.
16/715,532
Granted
Feb 8, 2022
Kind
B2
Abstract

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

Claims (39)

1. A method, comprising:

forming a first cavity in a bonding surface of a first substrate;

coating the first cavity with a barrier layer and a seed layer;

filling the first cavity with a conductive material having a first concentration of impurities to form a first conductive interconnect structure;

forming a planar bonding surface on the first substrate;

forming a second cavity in a bonding surface of a second substrate;

coating the second cavity with a barrier layer and a seed layer;

filling the second cavity with a conductive material having a second concentration of impurities to form a second conductive interconnect structure, the second concentration of impurities being different from the first concentration of impurities;

forming a planar bonding surface on the second substrate;

bonding the first substrate to the second substrate via direct bonding without adhesive; and

bonding the first conductive interconnect structure to the second conductive interconnect structure.

2. The method of claim 1 , further comprising partially filling the first cavity with the conductive material having the first concentration of impurities, and filling the remainder of the first cavity with the conductive material having a concentration of impurities that is different than the first concentration of impurities.

3. The method of claim 1 , further comprising partially filling the second cavity with the conductive material having the first concentration of impurities, and filling the remainder of the second cavity with the conductive material having a different concentration of impurities than the first concentration of impurities.

4. The method of claim 1 , further comprising bonding the first conductive interconnect structure to the second conductive interconnect structure at a temperature between 80° and 200° C.

5. The method of claim 1 , wherein the second concentration of impurities is at least one order of magnitude greater than the first concentration of impurities.

6. The method of claim 1 , wherein the impurities of the first concentration of impurities and/or the second concentration of impurities comprise one or more of: carbon, oxygen, nitrogen, and sulfur.

7. The method of claim 1 , further comprising forming a texture, including a grain orientation, of a bonding surface of the first conductive interconnect structure to be different from a texture, including a grain orientation, of a bonding surface of the second conductive interconnect structure.

8. The method of claim 1 , further comprising causing the impurities of the conductive material of the second conductive interconnect structure to diffuse into at least a portion of the conductive material of the first conductive interconnect structure at a bond line joining the second conductive interconnect structure to the first conductive interconnect structure.

9. The method of claim 1 , wherein the seed layer comprises sputtered copper having a texture orientation of {111}.

10. A method, comprising:

forming a first cavity in a bonding surface of a first substrate;

coating the first cavity with a barrier layer and a seed layer;

filling the first cavity with a conductive material to form a first conductive interconnect structure;

texturing a bonding surface of the first conductive interconnect structure to define a first texture on the bonding surface of the first conductive interconnect structure;

forming a second cavity in a bonding surface of a second substrate;

coating the second cavity with a barrier layer and a seed layer;

filling the second cavity with a conductive material to form a second conductive interconnect structure, a bonding surface of the second conductive interconnect structure having a second texture different from the first texture;

intimately bonding the first substrate to the second substrate; and

intimately bonding the bonding surface of the first conductive interconnect structure to the bonding surface of the second conductive interconnect structure.

11. The method of claim 10 , further comprising:

rinsing the bonding surface of the first and/or second conductive interconnect structures with diluted acid;

spin drying the first and/or second conductive interconnect structures in an oxygen ambient environment; and

rinsing and drying the bonding surface of the first and/or second conductive interconnect structures with deionized water.

12. The method of claim 10 , further comprising:

rinsing the bonding surface of the first and/or second conductive interconnect structures with a low acid concentrate copper sulfate solution;

spin drying the first and/or second conductive interconnect structures in an oxygen ambient environment;

rinsing the bonding surface of the first and/or second conductive interconnect structures with diluted acid; and

rinsing and drying the bonding surface of the first and/or second conductive interconnect structures with deionized water.

13. The method of claim 10 , further comprising bonding the first conductive interconnect structure to the second conductive interconnect structure at a temperature less than 200° C.

Assignments (3)
CHANGE OF NAME Recorded Oct 20, 2025
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 073173/0300 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2019
From: UZOH, CYPRIAN EMEKA
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 051294/0724 →