Highly scalable quantum control

1. A system comprising:

a quantum control data exchange circuit that comprises a plurality of interface circuits and memory, wherein a first interface circuit of the plurality of interface circuits is operable to:

receive a first message from a first quantum control pulse generation circuit of a plurality of quantum control pulse generation circuits, wherein the first message comprises a first opcode;

in response to the first opcode being a sync opcode, send a sync indication to a determined one or more others of the plurality of interface circuits;

in response to the first opcode being a write opcode, extract data from the first message and write the data to the memory; and

in response to the first opcode being a read opcode, read data from the memory and transmit the read data to the first quantum control pulse generation circuit.

2. The system of claim 1 , wherein the determined one or more others of the plurality of interface circuits are determined based on contents of a sync map in the memory.

3. The system of claim 2 , wherein the sync map indicates, for each of a plurality of time intervals, which of the plurality of quantum control pulse generation circuits are to be synchronized during that time interval, such that a first two or more of the plurality of quantum control pulse generation circuits can be synchronized during a first of the plurality of time intervals and a second two or more of the plurality of quantum control pulse generation circuits can be synchronized during a second of the plurality of time intervals.

4. The system of claim 1 , wherein the first interface circuit is operable to:

in response to the first opcode being a write opcode, detect whether the write opcode is a first-type write opcode or a second-type write opcode;

if the first opcode is a first-type write opcode, write the data to a first register of the memory; and

if the first opcode is a second-type write opcode, write the data to a second register of the memory.

5. The system of claim 1 , wherein:

the first interface circuit is operable to, in response to the first opcode being a read opcode, extract an index from the first message; and

determine a location within the memory from which to perform the read of the read data based on the index.

6. The system of claim 5 , wherein the index corresponds to from which of the plurality of quantum control pulse generation circuits the read data originated.

7. The system of claim 1 , wherein the first interface circuit is operable to:

in response to the first opcode being a read opcode, detect whether the read opcode is a first-type read opcode or a second-type read opcode;

if the read opcode is a first-type read opcode, read data from a first register of the memory; and

if the read opcode is a second-type read opcode, read data from a second register of the memory.

8. The system of claim 1 , comprising the plurality of quantum control pulse generation circuits.

9. The system of claim 8 , wherein:

the first quantum control pulse generation circuit comprises a first processor;

a second quantum control pulse generation circuit comprises a second processor;

the first quantum control pulse generation circuit is operable to:

receive, via the quantum control data exchange circuit, a value generated by the second processor;

determine phase, frequency, timing, and/or amplitude of a quantum control pulse based on a first value computed by the second processor; and

generate the quantum control pulse.

10. The system of claim 9 , wherein the first quantum control pulse generation circuit is operable to determine the phase, frequency, timing, and/or amplitude of the quantum control pulse based on a second value computed by the first processor.

11. A method comprising:

receive, by a first interface circuit of a plurality of interface circuits of a quantum control data exchange circuit, a first message from a first quantum control pulse generation circuit of a plurality of quantum control pulse generation circuits, wherein the first message comprises a first opcode;

in response to the first opcode being a sync opcode, sending, by the first interface circuit, a sync indication to a determined one or more others of the plurality of interface circuits;

in response to the first opcode being a write opcode, extracting, by the first interface circuit, data from the first message and writing, by the first interface circuit, the data to memory; and

in response to the first opcode being a read opcode, reading, by the first interface circuit, data from the memory and transmitting, by the first interface circuit, the read data to the first quantum control pulse generation circuit.

12. The method of claim 11 , comprising determining, by the first interface circuit, the determined one or more others of the plurality of interface circuits based on contents of a sync map in the memory.

13. The method of claim 12 , wherein the sync map indicates, for each of a plurality of time intervals, which of the plurality of quantum control pulse generation circuits are to be synchronized during that time interval, such that a first two or more of the plurality of quantum control pulse generation circuits can be synchronized during a first of the plurality of time intervals and a second two or more of the plurality of quantum control pulse generation circuits can be synchronized during a second of the plurality of time intervals.

14. The method of claim 11 , comprising:

in response to the first opcode being a write opcode, detecting, by the first interface circuit, whether the write opcode is a first-type write opcode or a second-type write opcode;

if the write opcode is a first-type write opcode, writing, by the first interface circuit, the data to a first register of the memory; and

if the write opcode is a second-type write opcode, writing, by the first interface circuit, the data to a second register of the memory.

15. The method of claim 11 , comprising:

in response to the first opcode being a read opcode, extracting, by the first interface circuit, an index from the first message; and

determining, by the first interface circuit, a location within the memory from which to perform the read of the read data based on the index.

16. The method of claim 15 , wherein the index corresponds to from which of the plurality of quantum control pulse generation circuits the read data originated.

17. The method of claim 11 , comprising:

in response to the first opcode being a read opcode, detecting, by the first interface circuit, whether the read opcode is a first-type read opcode or a second-type read opcode;

if the read opcode is a first-type read opcode, reading, by the first interface circuit, data from a first register of the memory; and

if the read opcode is a second-type read opcode, reading, by the first interface circuit, data from a second register of the memory.

18. The method of claim 11 , comprising:

the first quantum control pulse generation circuit comprises a first processor;

a second quantum control pulse generation circuit comprises a second processor;

the first quantum control pulse generation circuit is operable to:

receiving, by a first quantum control pulse generation circuit via the quantum control data exchange circuit, a value generated by a processor;

determining, by the first quantum control pulse generation circuit, phase, frequency, timing, and/or amplitude of a quantum control pulse based on a first value computed by the processor; and

generating, by the first quantum control pulse generation circuit, the quantum control pulse.

19. The method of claim 18 , comprising determining, by the first quantum control pulse generation circuit, the phase, frequency, timing, and/or amplitude of the quantum control pulse based on a second value computed by a second processor.