Detection of codewords

1. A method for detecting a code word, wherein the code word is a code word of one of at least two codes, comprising:

reading n states from memory cells of a memory, respectively;

determining the n states in a time domain for each of the at least two codes;

reading n additional states from further memory cells, respectively, and determining at least one reference value therefrom; and

taking the at least one reference value as a basis for determining which of the at least two codes is the correct code.

2. The method as claimed in claim 1 , comprising further processing the code word of the correct code.

3. The method as claimed in claim 1 , wherein each of the at least two codes is a k-out-of-n code having an identical value n and different values for k.

4. The method as claimed in claim 3 , wherein the at least two codes comprise a first k1-out-of-n code and a second k2-out-of-n code, wherein the reference value is determined such that it is based on a bit sequence corresponding to a k3-out-of-n code, wherein the value k3 lies between the values k1 and k2.

5. The method as claimed in claim 1 , wherein the n states are determined at least partly in parallel and/or at least partly simultaneously.

6. The method as claimed in claim 1 , wherein the n states are read from the further memory cells of the memory or from some other memory.

7. The method as claimed in claim 1 , wherein taking the at least one reference value as a basis for determining which of the at least two codes is the correct code comprises:

determining an integrated signal by integration of signals supplied by the n cells; and

comparing the integrated signal with the at least one reference value.

8. The method as claimed in claim 1 , wherein the at least one reference value is determined by:

determining a further integrated signal by integration of signals supplied by the n further cells.

9. The method as claimed in claim 1 , wherein the at least one reference value is determined for each read process of the cells from the memory.

10. The method as claimed in claim 1 , wherein the memory cells are read in groups of n memory cells.

11. The method as claimed in claim 1 , wherein the memory cells are complementary memory cells of a complementary memory.

12. The method as claimed in claim 1 , wherein the states are determined in the time domain by a number of k fastest states being determined.

13. The method as claimed in claim 12 , wherein the fastest states are 0-states.

14. The method as claimed in claim 12 , wherein the remaining states that do not belong to the k fastest states are correspondingly set.

15. The method as claimed in claim 1 , wherein the memory comprises at least one of the following memories:

floating gate cells;

PCRAM,

RRAM,

MRAM,

MONOS components,

nanocrystal cells, and

ROM.

16. A device for detecting a code word, wherein the code word is a code word of one of at least two codes, comprising a processing circuit configured to:

read n states from memory cells of a memory, respectively;

determine the n states in a time domain for each of the at least two codes;

read n additional states from further memory cells, respectively, and determining at least one reference value therefrom; and

take the at least one reference value as a basis for determining which of the at least two codes is the correct code.

17. A device for detecting a code word, wherein the code word is a code word of one of at least two codes, comprising:

means for reading n states from memory cells of a memory, respectively;

means for determining the n states in a time domain for each of the at least two codes;

means for reading n additional states from further memory cells and for determining at least one reference value on the basis of the states read from the further memory cells; and

means for determining which of the at least two codes is the correct code on the basis of the at least one reference value.

18. A non-transitory computer readable storage medium containing instructions which are loadable into a memory of a digital computer, wherein such instructions, upon execution, are suitable for carrying out a method, comprising:

reading n states from memory cells of a memory, respectively;

determining the n states in a time domain for each of the at least two codes;

reading n additional states from further memory cells, respectively, and determining at least one reference value therefrom; and

taking the at least one reference value as a basis for determining which of the at least two codes is the correct code.