IP Library › Granted Patent US 11,115,235
Granted Patent B2
US 11,115,235 · App. 16/717,030 · Granted Sep 7, 2021

Semiconductor device, communication systems and method for controlling the communication system

Inventors: Keiichiro Sano (Tokyo, JP); Jean Noel Mouthe (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H04L12/4015H04L7/0091H04L12/40013H04L12/40019H04L2012/40273
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Quick Facts
Patent No.
US 11,115,235
App. No.
16/717,030
Granted
Sep 7, 2021
Kind
B2
Abstract

A semiconductor device capable of improving the efficiencies of communication systems is provided. The semiconductor device comprises: an open period in which reception of data or transmission is allowed; a clock generation circuit defining a close period in which transmission of data and reception are not allowed; and a TSN controller connected to the clock generation circuit and performing transmission of data or reception, wherein the TSN controller performs semiconductor device or reception at another time than open period.

Claims (91)

1. A semiconductor device, comprising:

a clock generation circuit supplying time information; and

a controller inputting the time information, and transmitting or receiving data,

wherein the semiconductor device is permitted reception or transmission of the data during an open period, and is not permitted transmission or reception of the data during a close period,

wherein the open period and the close period are determined by the time information,

wherein the controller starts the transmission of the data earlier than a start of the open period, and

wherein the controller starts the reception of the data later than the start of the open period.

2. The semiconductor device according to claim 1 ,

wherein the controller comprises a delay time setting unit,

wherein the delay time setting unit is set with a transmission maximum delay time, a transmission minimum delay time, and a transmission delay time difference between the transmission maximum delay time and the transmission minimum delay time, in case of the data is transmitted to a first device connected to the controller via a bus, and

wherein the controller starts transmission of the data earlier than the start of the open period by a time corresponding to the transmission minimum delay time, and the controller ends the transmission of the data earlier than the end of the open period by a time corresponding to the transmission maximum delay time.

3. The semiconductor device according to claim 2 ,

wherein the delay time setting unit is set with a reception maximum delay time, a reception minimum delay time, and a reception delay time difference between the reception maximum delay time and the reception minimum delay time, in case of data is received from a second device connected to the bus, and

wherein the controller starts reception of data later than the start of the open period by a time corresponding to the reception minimum delay time, and the controller ends the reception of data later than the end of the open period by a time corresponding to the reception maximum delay time.

4. The semiconductor device according to claim 3 ,

wherein the controller comprises a first buffer in which data to be transmitted is stored, and a second buffer in which received data is stored,

wherein the transmission minimum delay time is a minimum delay time in case of data is transmitted from the first buffer to the first device,

wherein the transmission maximum delay time is a maximum delay time in case of data is transmitted from the first buffer to the first device

wherein the reception minimum delay time is a minimum delay time in case of data is transmitted from the second device to the second buffer, and

wherein the reception maximum delay time is a maximum delay time in case of data is transmitted from the second device to the second buffer.

5. The semiconductor device according to claim 4 ,

wherein the first buffer and the second buffer are the same buffer, and

wherein the first device and the second device are the same device.

6. The semiconductor device according to claim 1 ,

wherein the controller comprises a delay time setting unit,

wherein the delay time setting unit is set with a reception maximum delay time, a reception minimum delay time, and a reception delay time difference between the transmission maximum delay time and the transmission minimum delay time, in case of data is received from a device connected to the controller via a bus, and

wherein the controller starts reception of the data later than the start of the open period by a time corresponding to the reception minimum delay time, and the controller ends reception of the data later than the end of the open period by a time corresponding to the reception maximum delay time.

7. The semiconductor device according to claim 1 , further comprising;

an input/output circuit transmitting the data to outside of the semiconductor device, and receiving the data from the semiconductor device,

wherein the controller starts the transmission of the data to the input/output circuit earlier than a start of the open period.

8. A communication system comprising:

a first device connected to a first bus; and

a second device connected to the first device via the first bus,

wherein the first device comprises;

a first clock generation circuit supplying time information; and

a controller inputting the time information, and

transmitting or receiving data,

wherein based on the time information, an open period and a close period and are determined,

wherein first device is permitted reception or transmission of data during the open period, and is not permitted transmission or reception of the data during the close period,

wherein the controller starts the transmission of the data earlier than a start of the open period, and

wherein the controller starts the reception of the data later than the start of the open period.

9. The communication system according to claim 8 ,

wherein the controller comprises a delay time setting unit,

wherein the delay time setting unit is set with a transmission maximum delay time, a transmission minimum delay time, and a transmission delay time difference between the transmission maximum delay time and the transmission minimum delay time, in case of data is transmitted to a first device connected to the controller via a bus, and

wherein the controller starts transmission of the data earlier than the start of the open period by a time corresponding to the transmission minimum delay time, and the controller ends transmission of the data earlier than the end of the open period by a time corresponding to the transmission maximum delay time.

10. The communication system according to claim 9 ,

wherein the delay time setting unit is set with a reception maximum delay time, a reception minimum delay time, and a reception delay time difference between the reception maximum delay time and the reception minimum delay time, in case of data is received from a second device, and

wherein the controller starts reception of data later than the start of the open period by a time corresponding to the reception minimum delay time, and the controller ends reception of data later than the end of the open period by a time corresponding to the reception maximum delay time.

11. The communication system according to claim 10 ,

wherein the second device comprises a second clock generation circuit for measuring time in synchronization with the first clock generation circuit, and

wherein the second device is permitted to receive or transmit data during the open period defined by the second clock generation circuit.

12. The communication system according to claim 11 ,

wherein the open period defined by the first clock generation circuit and the open period defined by the second clock generation circuit are overlapped.

13. The communication system according to claim 8 ,

wherein the controller comprises a delay time setting unit,

wherein the delay time setting unit is set with a reception maximum delay time, a reception minimum delay time, and a reception delay time difference between the reception maximum delay time and the reception minimum delay time, in case of data is received from the second device, and

wherein the controller starts reception of data later than the start of the open period by a time corresponding to the reception minimum delay time, and the controller ends the reception of data later than the end of the open period by a time corresponding to the reception maximum delay time.

14. A method for controlling a communication system:

a first device; and

a second device coupled to the first device via a bus,

wherein the first device comprises:

a first clock generation circuit defining an open period in which data reception or transmission is permitted and a close period in which data transmission or reception is not permitted;

a delay time setting unit; and

a controller performing transmission or reception of data in a period other than the open period based on time information set in the delay time setting unit,

wherein the second device comprises:

a second clock generation circuit defining an open period in which data reception or transmission is permitted and a close period in which data transmission or reception is not permitted,

a training step for determining the time information set in the delay time setting unit; and

an operating step in which transmission of data or reception of data is performed between the first device and the second device after the training step.

15. The method for controlling a communication system according to claim 14 ,

wherein the training step includes:

a reception delay time obtaining step for obtaining a delay time in case of receiving the data by the first device; and

a setting step for setting time information related to the delay time obtained by the reception delay time obtaining step in the delay time setting unit,

wherein the reception delay time obtaining step includes; receiving a reception training data including time information from the second device by the first device, and

obtaining the delay time by the first device based on the time information included in the reception training data and based on a time measured by the first clock generation circuit in case of receiving the reception training data.

16. The method for controlling a communication system according to claim 15 ,

wherein the training step includes:

a transmission delay time obtaining step for obtaining a delay time in case of transmitting the data by the first device; and

a setting step for setting time information related to the delay time obtained by the transmission delay time obtaining step in the delay time setting unit,

wherein the transmission delay time obtaining step includes;

transmitting a transmission training data including time information from the first device to the second device; and

obtaining the delay time by the second device based on the time information included in the transmission training data and based on a time measured by the second clock generation circuit in case of receiving the transmission training data.

17. The method for controlling a communication system according to claim 16 , further comprising the step of:

before the step of the training step,

a time setting step for synchronizing the first clock generation circuit and the second clock generation circuit.

18. The method for controlling a communication system according to claim 14 ,

wherein the training step includes:

a transmission delay time obtaining step for obtaining a delay time in case of transmitting the data by the first device; and

a setting step for setting the delay time obtained by the transmission delay time obtaining step in the delay time setting unit,

wherein the transmission delay time obtaining step includes;

transmitting a transmission training data including time information from the first device to the second device; and

obtaining the delay time by the second device based on the time information included in the transmission training data and based on a time measured by the second clock generation circuit in case of receiving the transmission training data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: SANO, KEIICHIRO; NOEL MOUTHE, JEAN
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 051318/0657 →
Priority Claims (1)
JP JP2018-244393 · Dec 27, 2018 · national
Continuity (1)
Related Publication 20200213148A1 · Jul 2, 2020