Semiconductor device and method
A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
1. A semiconductor device comprising:
a first fin and a second fin extending from a substrate;
a gate stack disposed over the first fin and the second fin;
an epitaxial source/drain region disposed adjacent the gate stack and over the first fin and the second fin;
an inter-layer dielectric (ILD) layer having a first portion and a second portion, the first portion disposed over the epitaxial source/drain region, the second portion disposed under the epitaxial source/drain region, the second portion having a void region therein, the void region exposing a first surface of the epitaxial source/drain region; and
a source/drain contact extending through the first portion of the ILD layer, the source/drain contact contacting a second surface of the epitaxial source/drain region.
2. The semiconductor device of claim 1 further comprising:
an isolation region disposed between the first fin and the second fin, the second portion of the ILD layer disposed between the isolation region and the epitaxial source/drain region.
3. The semiconductor device of claim 2 , wherein the isolation region has an upper surface that is concave or v-shaped.
4. The semiconductor device of claim 2 , wherein the void region is separated from the isolation region by the ILD layer.
5. The semiconductor device of claim 1 , wherein the first surface and the second surface of the epitaxial source/drain region each have an irregular topology.
6. The semiconductor device of claim 1 , wherein the first surface and the second surface of the epitaxial source/drain region each have a planar topology.
7. The semiconductor device of claim 1 , wherein the epitaxial source/drain region comprises a single semiconductor material extending continuously between the first fin and the second fin.
8. A semiconductor device comprising:
an isolation region over a substrate;
a first fin extending from between neighboring portions of the isolation region;
a gate stack disposed over the first fin and the isolation region;
a first epitaxial source/drain region disposed adjacent the gate stack and over the first fin;
an inter-layer dielectric (ILD) layer having a first portion and a second portion, the first portion disposed over the first epitaxial source/drain region, the second portion disposed between the first epitaxial source/drain region and the isolation region, the second portion having a void region therein, the void region adjoining a first surface of the first epitaxial source/drain region, the void region being separated from the isolation region by the ILD layer; and
a source/drain contact extending through the first portion of the ILD layer, the source/drain contact connected to the first epitaxial source/drain region.
9. The semiconductor device of claim 8 further comprising:
a second fin extending from between neighboring portions of the isolation region, the first epitaxial source/drain region disposed over the first fin and the second fin.
10. The semiconductor device of claim 9 , wherein the first surface of the first epitaxial source/drain region has an irregular topology.
11. The semiconductor device of claim 9 , wherein the first surface of the first epitaxial source/drain region has a planar topology.
12. The semiconductor device of claim 9 , wherein the first epitaxial source/drain region comprises a single continuous semiconductor material extending between the first fin and the second fin.
13. The semiconductor device of claim 8 further comprising:
a second fin extending from between neighboring portions of the isolation region; and
a second epitaxial source/drain region disposed adjacent the gate stack and over the second fin, the void region adjoining a second surface of the second epitaxial source/drain region.
14. The semiconductor device of claim 13 , wherein the void region is disposed under contacting portions of the first epitaxial source/drain region and the second epitaxial source/drain region.
15. A method comprising:
forming a first fin and a second fin extending from a substrate;
depositing an isolation region between the first fin and the second fin;
growing an epitaxial source/drain region on the first fin and the second fin;
depositing an inter-layer dielectric (ILD) layer over the substrate, a void region being formed in the ILD layer during the depositing, the void region being laterally disposed between the first fin and the second fin, the void region exposing a first surface of the epitaxial source/drain region;
etching an opening in the ILD layer to expose a second surface of the epitaxial source/drain region; and
forming a source/drain contact in the opening, the source/drain contact connected to the epitaxial source/drain region.
16. The method of claim 15 , wherein the epitaxial source/drain region comprises a single continuous semiconductor material.
17. The method of claim 15 further comprising:
etching the isolation region to form an upper surface that is concave or v-shaped, a lower boundary of the void region being disposed closer to the substrate than an apex of the upper surface of the isolation region.
18. The method of claim 15 , wherein the first surface of the epitaxial source/drain region has an irregular topology.
19. The method of claim 15 , wherein the first surface of the epitaxial source/drain region has a planar topology.