Computational units for element approximation
Herein are disclosed computation units for element approximation. A computation unit may include a first circuit to compute a first projection π of an input element x i from a first range to a second range. In the first circuit, the input element x i may have a first format and the projected element y i may have a second format. In addition, in the first circuit, the second format may have more bits than the first format. The computation unit may further include a second circuit operatively coupled to the first circuit to produce a reduction z i in the first format using the projected element y i in the second format. The computation unit may also include a third circuit operatively coupled to the second circuit to compute a second projection ρ of the reduction z i from the second range to the first range to produce an approximation w i .
1. A computation unit, comprising:
a first circuit to compute a first projection π of an input element x i from a first range to a second range, the input element x i having a first format and a projected element y i having a second format, the second format having more bits than the first format;
a second circuit operatively coupled to the first circuit to produce a reduction z i in the first format using the projected element y i in the second format; and
a third circuit operatively coupled to the second circuit to compute a second projection ρ of the reduction z i from the second range to the first range to produce an approximation w i .
2. The computation unit of claim 1 , wherein the second range comprises a boundary of the first format.
3. The computation unit of claim 1 , wherein the first projection π shifts at least one bit of the input element x i in the first format to produce the projected element y i in the second format.
4. The computation unit of claim 3 , wherein the first circuit shifts the at least one bit of the input element x i based on an exponent difference between one or more exponent bits of the input element x i and one or more exponent bits of a shift value S to produce the second format.
5. The computation unit of claim 1 , wherein the second projection ρ is an inverse operation of the first projection π.
6. The computation unit of claim 1 , wherein the approximation w i may be an over-approximation or an under-approximation of the input element x i .
7. The computation unit of claim 6 , wherein the first circuit:
when computing an over-approximation, selects a larger shift value if the input element x i is greater than zero and selects a smaller shift value if the input element x i is less than zero; and
when computing an under-approximation, selects a smaller shift value if the input element x i is greater than zero and selects a larger shift value if the input element x i is less than zero.
8. The computation unit of claim 7 , wherein the larger shift value corresponds to a boundary of the first format and the smaller shift value corresponds to a boundary of the first range.
9. The computation unit of claim 7 , wherein:
when computing the over-approximation, the second range corresponds to a negative boundary of the first format; and
when computing the under-approximation, the second range corresponds to a positive boundary of the first format.
10. The computation unit of claim 1 , wherein the first circuit selects a shift value S to apply in the first projection π.
11. The computation unit of claim 10 , wherein the first circuit:
when computing an over-approximation, subtracts the shift value S from the input element x i to produce a difference (x i −S); and
when computing an under-approximation, adds the shift value S to the input element x i to produce a sum (x i +S).
12. The computation unit of claim 11 , wherein the third circuit:
when computing the over-approximation, adds the shift value to a rounded difference (x i −S); and
when computing the under-approximation, subtracts the shift value from a rounded sum (x i +S).
13. The computation unit of claim 11 , wherein the first circuit selects the shift value S based on the first format of the input element x i .
14. The computation unit of claim 11 , wherein the first circuit bypasses an input element x i , if one or more bits of a mantissa of the input element x i is zero.
15. The computation unit of claim 1 , wherein the second circuit truncates one or more bits of the projected element y i to produce the reduction z i .
16. The computation unit of claim 15 , wherein truncating the one or more bits rounds the projected element y i towards zero.
17. The computation unit of claim 1 , further comprising a fourth circuit, wherein the fourth circuit selects an output from the input element x i and the approximation w i .
18. The computation unit of claim 17 , wherein the fourth circuit computes an absolute value of the input element x i .
19. The computation unit of claim 18 , wherein the fourth circuit:
determines a boundary of the first range; and
compares the absolute value to the boundary,
wherein, the fourth circuit:
if the absolute value is greater than the boundary, selects the input element x i as the output; and
if the absolute value is less than the boundary, selects the approximation w i as the output.
20. A re-configurable processor, comprising:
a first circuit to compute a first projection π of an input element x i from a first range to a second range, the input element x i having a first format and a projected element y i having a second format, the second format having more bits than the first format;
a second circuit operatively coupled to the first circuit to produce a reduction z i in the first format using the projected element y i in the second format; and
a third circuit operatively coupled to the second circuit to compute a second projection ρ of the reduction z i from the second range to the first range to produce an approximation w i .
21. A method, comprising:
computing, by a first circuit, a first projection π of an input element x i from a first range to a second range, the input element x i having a first format and a projected element y i having a second format, the second format having more bits than the first format;
producing, by a second circuit operatively coupled to the first circuit, a reduction z i in the first format using the projected element y i in the second format; and
computing, by a third circuit operatively coupled to the second circuit, a second projection ρ of the reduction z i from the second range to the first range to produce an approximation w i .