Patent Assignment
Reel/Frame 070892/0001
Intellectual Property Security Agreement
Recorded: 2025-04-18
Pages: 30
Assignor
SAMBANOVA SYSTEMS, INC.
Executed: 2025-04-18
Assignee
SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
222 2ND STREET, FLOORS 17-20, SAN FRANCISCO, CALIFORNIA, 94105
Covered Properties
(249)
Lossless Tiling in Convolution Networks - Padding and Re-Tilling at Section Boundaries
Application:
17/364,141 →
Publication:
US 2022/0309318
Lossless Tiling in Convolution Networks - Section Boundaries
Lossless Tiling in Convolution Networks - Data Flow Logic
Calculating a Floating-Point Function using Multiple Lookup Tables
Matrix Multiplication on Coarse-grained Computing Grids
Application:
17/824,830 →
Publication:
US 2023/0244748
Dependency-Aware Server Processing of Dataflow Applications
Application:
17/847,045 →
Publication:
US 2023/0205580
System of Heterogeneous Reconfigurable Processors for the Data-Parallel Execution of Applications
Application:
17/941,947 →
Publication:
US 2023/0237013
Floating Point Accumulater with a Single Layer of Shifters in the Significand Feedback
Execution State Management
Buffer Fusion and Layout Optimization
Application:
17/987,628 →
Publication:
US 2023/0409233
Estimating Throughput for Placement Graphs for a Reconfigurable Dataflow Computing System
Application:
17/990,556 →
Publication:
US 2023/0162032
Hot-Plug Events In A Pool Of Reconfigurable Data Flow Resources
Elevated Isolation of Reconfigurable Data Flow Resources in Cloud Computing
System and Method for User Interactive Pipelining of a Computing Application
User Interactive Pipelining of a Computing Application Using a Buffer Pipeline Programming Interface
Application:
18/087,125 →
Publication:
US 2023/0205614
Compiler-Based Input Synchronization for Processor with Variant Stage Latencies
Database Driven Place and Route for Coarse-Grain Reconfigurable Architectures
Iterative Database Driven Place and Route for Coarse-Grain Reconfigurable Architectures
Application:
18/092,439 →
Publication:
US 2024/0220766
Training a Graph Neural Network for Database Driven Place and Route
Application:
18/092,440 →
Publication:
US 2024/0220803
Dataflow Architecture Processor Statically Reconfigurable to Perform N-Dimensional Affine Transformation in a Tiled Manner
Application:
18/095,128 →
Publication:
US 2024/0232127
Dataflow Architecture Processor Statically Reconfigurable to Perform N-Dimensional Affine Transformation
Dataflow Architecture Processor Statically Reconfigurable to Perform N-Dimensional Affine Transformation in Parallel Manner by Replicating Copies of Input Image Across Scratchpad Memory Banks
Application:
18/095,134 →
Publication:
US 2024/0232128
Dataflow Architecture Processor Statically Reconfigurable to Perform N-Dimensional Affine Transformation in Parallel Manner by Replicating Copies of Input Image Across Multiple Scratchpad Memories
Method and Apparatus for Data Transfer Between Accessible Memories of Multiple Processors in a Heterogeneous Processing System Using Two Memory to Memory Transfer Operations
Matrix Summation Using Integrated Matrices
Application:
18/102,658 →
Publication:
US 2024/0256631
Configurable Access to a Reconfigurable Processor by a Virtual Function
Configurable Access to a Multi-Die Reconfigurable Processor by a Virtual Function
Exploiting Shared Dimensions in Matrix Computations
Application:
18/105,695 →
Publication:
US 2023/0252106
Fault Management in a Reconfigurable Dataflow Architecture
Direct Access to External Storage from a Reconfigurable Processor
Overlapping Gradient Synchronization In Machine Learning
Application:
18/109,080 →
Publication:
US 2023/0259823
Critical Stage Optimization for Reconfigurable Architectures
Handling Interrupts from a Virtual Function in a System with a Multi-Die Reconfigurable Processor
Handling Interrupts from a Virtual Function in a System with a Reconfigurable Processor
Bandwidth-Aware Computational Graph Mapping
Compiler Optimization of Dataflow Applications Using Mixed Integer Equations
Application:
18/128,076 →
Publication:
US 2023/0315802
Searching Neural Network Pipelines Based on Named Matrix Dimensions
Application:
18/128,104 →
Publication:
US 2023/0315414
Optimizing Tensor Tiling in Neural Networks Based on a Tiling Cost Model
Application:
18/129,714 →
Publication:
US 2023/0315410
Iterative Compilation to Optimize Translation in Reconfigurable Dataflow Architectures
Tensor Checkpoint Optimization in Dataflow Computing Applications
Operation Fusion in Nested Meta-pipeline Loops
Integrated Circuit That Mitigates Inductive-Induced Voltage Droop
Application:
18/132,390 →
Publication:
US 2024/0085965
Integrated Circuit That Mitigates Inductive-Induced Voltage Droop Using Compute Unit Group Identifiers
Compiler That Generates Configuration Information for Configuring an Integrated Circuit to Mitigate Inductive-Induced Voltage Droop
Integrated Circuit That Mitigates Inductive-Induced Voltage Overshoot
System for the Remote Execution of Applications
Compile Time Logic for Detecting and Resolving Memory Layout Conflicts
Application:
18/136,321 →
Publication:
US 2023/0376292
Convolution Calculation Engine
Application:
18/144,818 →
Publication:
US 2024/0378259
Convolution Calculation Engine Using Look-Up Tables for Address Calculation
Application:
18/144,819 →
Publication:
US 2024/0378147
Top Level Network and Array Level Network for Reconfigurable Data Processors
Intelligent Data Conversion in Dataflow and Data Parallel Computing Systems
Application:
18/200,210 →
Publication:
US 2023/0385103
Load Balancing System for the Execution of Applications on Reconfigurable Processors
Graph Spatial Split
Forward-style Gradient GeMMs
Fully Scannable Memory Arrays
Application:
18/207,482 →
Publication:
US 2024/0412797
All Reduce Across Multiple Reconfigurable Dataflow Processors
Application:
18/208,048 →
Publication:
US 2023/0409520
Runtime Virtualization of Reconfigurable Data Flow Resources
Handling Dynamic Tensor Lengths in a Reconfigurable Processor That Includes Multiple Memory Units
Estimating a Cost of Implementing an Operation Unit Graph on a Reconfigurable Processor
Application:
18/221,678 →
Publication:
US 2024/0020170
Estimating a Scaled Cost of Implementing an Operation Unit Graph on a Reconfigurable Processor
Operating a Cost Estimation Tool for Placing and Routing an Operation Unit Graph on a Reconfigurable Processor
Matrix Summation Using Integrated Matrices with Scalar Injection
Application:
18/225,339 →
Publication:
US 2023/0367844
Using Integrated Matrices in Back Propagation Computations
Application:
18/225,365 →
Publication:
US 2023/0367845
Sorting the Nodes of an Operation Unit Graph for Implementation in a Reconfigurable Processor
Placement Method Based On A Sorted Operation Unit Graph For An Iterative Placement And Routing On A Reconfigurable Processor
Application:
18/225,865 →
Publication:
US 2024/0036871
Routing Method Based On A Sorted Operation Unit Graph For An Iterative Placement And Routing On A Reconfigurable Processor
Flexible Classes for Statically Compiled Classification Graphs
Application:
18/234,358 →
Publication:
US 2025/0061313
Multiple Contexts for a Compute Unit in a Reconfigurable Data Processor
Multiple Contexts for a Memory Unit in a Reconfigurable Data Processor
Application:
18/236,811 →
Publication:
US 2024/0069770
Finite State Machine for Context Switching in a Reconfigurable Data Processor
Application:
18/237,089 →
Publication:
US 2024/0069959
Intelligent Graph Execution and Orchestration Engine for a Reconfigurable Data Processor
Application:
18/243,994 →
Publication:
US 2024/0338340
Debugging Framework for a Reconfigurable Data Processor
Estimating Resource Costs for Computing Tasks for a Reconfigurable Dataflow Computing System
Application:
18/367,764 →
Publication:
US 2024/0086235
Dynamic Exponent Bias Method for Neural Network Training
Application:
18/481,422 →
Publication:
US 2025/0117647
Concurrent Matrix Computations Using Split Matrices with Mulitiple Reconfigurable Processors
Application:
18/378,278 →
Publication:
US 2024/0037181
Concurrent Matrix Computations Using Split Matrices with Mulitiple Stage Processors
Application:
18/378,293 →
Publication:
US 2024/0037182
Reconfigurable Dataflow Unit with Streaming Write Functionality
Reconfigurable Dataflow Unit Having Remote Fifo Management Functionality
Method and System to Determine Execution Inefficiencies in Dataflow Programs
Analysis Assistant for Determining Execution Inefficiencies in Dataflow Programs
Lossless Tiling in Convolution Networks - Tiling Configuration Between Two Sections
Duplication of Tensors for Memory Allocation in a Reconfigurable Data Processor
Application:
18/522,787 →
Publication:
US 2025/0053518
Method for Scanning a Memory Array
Configuration File Generation For Fracturable Data Path In A Coarse-Grained Reconfigurable Processor
Application:
18/583,845 →
Publication:
US 2024/0192935
Computer System with Reconfigurable Processors
Data Transfer in Dataflow Computing Systems Using an Intelligent Dynamic Transfer Engine
Application:
18/614,639 →
Publication:
US 2024/0231903
Method and System for Integrating Buffer Views into Buffer Access Operations in Reconfigurable Computing Environments
Application:
18/623,180 →
Publication:
US 2024/0241844
Flip-Flop With Trigger Edge Determined By Latch Order
Application:
18/624,056 →
Publication:
US 2024/0250670
Multiple Test Modes for a Memory in an Integrated Circuit
Dataflow Graph Performance Debugger And Design Rule Checker For CGRA
Application:
18/632,236 →
Publication:
US 2024/0345936
Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors
Application:
18/635,114 →
Publication:
US 2024/0273057
Hang Detection In A Coarse Grained Reconfigurable Architecture Processor
Application:
18/657,619 →
Publication:
US 2024/0385920
Network Health Monitor Within A Coarse Grained Reconfigurable Architecture Processor
Switches With A Watchdog Timer For Use In An Internal Network Of A Processor
Application:
18/657,704 →
Publication:
US 2024/0388519
Failure Recovery In A Distributed Coarse Grained Reconfigurable Architecture
Method And System For Unloading Configuration Data In A Reconfigurable Processor Array
High-Bandwidth Power Estimator
Two-Level Arbitration in a Computing System
Data Processing System with Link-Based Resource Allocation for Reconfigurable Processors
Configuration Data Store in a Reconfigurable Data Processor Having Two Access Modes
Coarse-Grained Reconfigurable Processor Array with Optimized Buffers
Application:
18/776,229 →
Publication:
US 2024/0370240
Reconfigurable Processing Element for a Systolic Array
Application:
18/779,442 →
Publication:
US 2025/0028785
Implementing Matrix Multiplication on a Systolic Array with Reconfigurable Processing Elements
Application:
18/779,448 →
Publication:
US 2025/0028786
Method to Reset Configurable Units in a Reconfigurable Processor
System and Method for Optimizing Data-Transfer Among Multiple Compute Units in a Data-Parallel Computing System
Application:
18/794,143 →
Publication:
US 2024/0394218
Hardware Layer-by-Layer Program Control in a Reconfigurable Dataflow Processor
Application:
18/824,846 →
Publication:
US 2025/0077239
System for Implementing Operations Having Dynamically-Sized Data Structures on a Reconfigurable Processor
Application:
18/884,690 →
Publication:
US 2025/0004971
Coupling Operations on Dynamically-Sized Data Structures in Data Flow Architectures
Application:
18/884,707 →
Publication:
US 2025/0004972
Memory Unit Partitioning for Reconfigurable Dataflow Computers
Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid
Buffer Splitting Based on Cost
Application:
18/944,624 →
Publication:
US 2025/0068587
Port Arbitration in Switch Networks for Dataflow Computer Systems
Application:
18/966,107 →
Publication:
US 2025/0094376
Computational Nodes Fusion in a Reconfigurable Data Processor
Application:
18/974,291 →
Publication:
US 2025/0103550
Data Access in a Heterogeneous Processing System with Multiple Processors
Application:
18/984,852 →
Publication:
US 2025/0117336
Configuration Load of a Reconfigurable Data Processor
Configuration Unload of a Reconfigurable Data Processor
Virtualization of a Reconfigurable Data Processor
Matrix Normal/Transpose Read and a Reconfigurable Data Processor Including Same
Control Flow Barrier and Reconfigurable Data Processor
Quiesce Reconfigurable Data Processor
Compiler Flow Logic for Reconfigurable Architectures
Sigmoid Function in Hardware and a Reconfigurable Data Processor Including Same
Performance Estimation-Based Resource Allocation for Reconfigurable Architectures
Computation Units for Functions Based on Lookup Tables
Look-Up Table with Input Offsetting
Computational Units for Batch Normalization
Computational Units for Element Approximation
Computationally Efficient Softmax Loss Gradient Backpropagation
Virtualization of a Reconfigurable Data Processor
Computationally Efficient General Matrix-Matrix Multiplication (Gemm)
Anti-Congestion Flow Control for Reconfigurable Processors
Runtime Virtualization of Reconfigurable Data Flow Resources
Runtime Patching of Configuration Files
Compile Time Logic for Detecting Streaming Compatible and Broadcast Compatible Data Access Patterns
Patent:
11,237,971 →
Application:
17/023,015 →
Systems and Methods for Memory Layout Determination and Conflict Resolution
Configuration of a Reconfigurable Data Processor using Sub-Files
Intra-Node Buffer-Based Streaming for Reconfigurable Processor-As-A-Service (RPaaS)
Patent:
11,182,264 →
Application:
17/127,818 →
Inter-Node Buffer-Based Streaming for Reconfigurable Processor-As-A-Service (RPaaS)
Patent:
11,182,221 →
Application:
17/127,929 →
Instrumentation Profiling for Reconfigurable Processors
Patent:
11,126,574 →
Application:
17/175,289 →
Time-Multiplexed use of Reconfigurable Hardware
Resource Allocation for Reconfigurable Processors
Patent:
11,200,096 →
Application:
17/214,768 →
Universal Rail Kit
Patent:
11,191,182 →
Application:
17/216,509 →
Tensor Partitioning and Partition Access Order
Patent:
11,204,889 →
Application:
17/216,647 →
Multi-Headed Multi-Buffer for Buffering Data for Processing
Patent:
11,366,783 →
Application:
17/216,650 →
Lossless Tiling in Convolution Networks - Tiling Configuration
Patent:
11,195,080 →
Application:
17/216,651 →
Lossless Tiling in Convolution Networks - Section Boundaries
Patent:
11,227,207 →
Application:
17/216,652 →
Lossless Tiling in Convolution Networks - Read-Modify-Write in Backward Pass
Patent:
11,250,061 →
Application:
17/216,654 →
Lossless Tiling In Convolution Networks - Weight Gradient Calculation
Patent:
11,232,360 →
Application:
17/216,655 →
Lossless Tiling In Convolution Networks - Padding Before Tiling, Location-Based Tiling, And Zeroing-Out
Patent:
11,263,170 →
Application:
17/216,657 →
Quiesce Reconfigurable Data Processor
Compiler Flow Logic for Reconfigurable Architectures
Dual Cycle Tensor Dropout in a Neural Network
Patent:
11,328,209 →
Application:
17/337,080 →
Memory Efficient Dropout, with Reordering of Dropout Mask Elements
Patent:
11,256,987 →
Application:
17/337,126 →
Variable-Length Clock Stretcher with Correction for Glitches Due to Finite DLL Bandwidth
Patent:
11,323,124 →
Application:
17/338,620 →
Variable-Length Clock Stretcher with Correction for Glitches due to Phase Detector Offset
Patent:
11,239,846 →
Application:
17/338,625 →
Variable-Length Clock Stretcher with Correction for Digital DLL Glitches
Patent:
11,290,113 →
Application:
17/338,626 →
Variable-Length Clock Stretcher with Passive Mode Jitter Reduction
Patent:
11,290,114 →
Application:
17/338,629 →
Lossless Tiling in Convolution Networks - Tiling Configuration for a Sequence of Sections of a Graph
Systems and Methods for Editing Topology of a Reconfigurable Data Processor
Defect Repair for a Reconfigurable Data Processor for Homogeneous Subarrays
Patent:
11,556,494 →
Application:
17/378,342 →
Defect Repair Circuits for a Reconfigurable Data Processor
Patent:
11,327,771 →
Application:
17/378,391 →
Routing Circuits for Defect Repair for a Reconfigurable Data Processor
Patent:
11,409,540 →
Application:
17/378,399 →
Dataflow Function Offload to Reconfigurable Processors
Dataflow All-Reduce for Reconfigurable Processor Systems
Patent:
11,237,880 →
Application:
17/379,924 →
Lossless Tiling In Convolution Networks - Backward Pass
Lossless Tiling in Convolution Networks - Materialization of Tensors
Floating Point Multiply-Add, Accumulate Unit with Carry-Save Accumulator
Patent:
11,429,349 →
Application:
17/397,241 →
Variable-Length Clock Stretcher with Combiner Timing Logic
Patent:
11,334,109 →
Application:
17/405,913 →
Floating Point Multiply-Add, Accumulate Unit with Combined Alignment Circuits
Patent:
11,366,638 →
Application:
17/465,558 →
Method and Circuit for Row Scannable Latch Array
Method and Circuit for Scan Dump of Latch Array
Tensor Partitioning and Partition Access Order
Compile Time Instrumentation of Data Flow Graphs
Instrumentation Networks for Data Flow Graphs
Control Barrier Network for Reconfigurable Data Processors
Built-In Self-Test for Processor Unit with Combined Memory and Logic
Patent:
11,449,404 →
Application:
17/501,969 →
Array of Processor Units with Local BIST
Patent:
11,428,737 →
Application:
17/503,227 →
Sparse Matrix Multiplier in Hardware and a Reconfigurable Data Processor Including Same
Patent:
11,443,014 →
Application:
17/520,290 →
Runtime Execution of Configuration Files on Reconfigurable Processors with Varying Configuration Granularity
Inter-Processor Execution of Configuration Files on Reconfigurable Processors Using Smart Network Interface Controller (Smartnic) Buffers
Runtime Execution of Functions Across Reconfigurable Processor
Inter-Node Execution of Configuration Files on Reconfigurable Processors Using Smart Network Interface Controller (Smartnic) Buffers
Inter-Node Execution of Configuration Files on Reconfigurable Processors Using Network Interface Controller (Nic) Buffers
Interconnect-Based Resource Allocation for Reconfigurable Processors
Efficient Deconfiguration of a Reconfigurable Data Processor
Floating Point Multiply-Add, Accumulate Unit with Exception Processing
Fast Clocked Storage Element
Hot-plug Events in a Pool of Reconfigurable Data Flow Resources
Patent:
11,487,694 →
Application:
17/554,913 →
Compile Time Logic for Inserting a Buffer Between a Producer Operation Unit and a Consumer Operation Unit in a Dataflow Graph
Training a Neural Network Using a Non-Homogenous Set of Reconfigurable Processors
Executing a Neural Network Graph Using a Non-Homogenous Set of Reconfigurable Processors
Independent Control of Multiple Concurrent Application Graphs in a Reconfigurable Data Processor
Tensor Dropout Using a Mask Having a Different Ordering Than the Tensor
Tensor Dropout in a Neural Network
Lossless Tiling in Convolution Networks - Section Cuts
Lossless Tiling in Convolution Networks - Graph Metadata Generation
High-Performance Flip-Flop
Patent:
11,552,622 →
Application:
17/702,295 →
Lossless Tiling in Convolution Networks - Resetting Overlap Factor to Zero at Section Boundaries
Defect Avoidance in a Multidimensional Array of Functional Configurable Units
Switch for Routing Data in an Array of Functional Configurable Units
Dependency-Based Queuing of Work Requests in Dataflow Applications
Determining and Using Memory Unit Partitioning Solutions for Reconfigurable Dataflow Computing Systems
Performance Estimation-Based Resource Allocation for Reconfigurable Architectures
Partitioning Dataflow Operations for a Reconfigurable Computing System Through Recursive Candidate Generation
Dynamic Destination Id in an Array Level Network of a Reconfigurable Dataflow Processor
Patent:
12,267,256 →
Application:
17/894,134 →
System for Executing an Application on Heterogeneous Reconfigurable Processors
Single "a" Latch with an Array of "B" Latches
Floating-Point Accumulator
Skip Buffer Splitting
Integrating Buffer Views into Buffer Access Operations in a Coarse-grained Reconfigurable Computing Environment
Force Quit of Reconfigurable Processor
Fractional Force-Quit for Reconfigurable Processors
Merging Buffer Access Operations in a Coarse-grained Reconfigurable Computing System
Access To Intermediate Values In A Dataflow Computation
Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid
Non-Uniform Memory Interleave Method
High-Bandwidth Power Estimator for Ai Accelerator
Delay-Locked Loop with Widened Lock Range
Determining Internodal Processor Interconnections in a Data-Parallel Computing System
Fast Clocked Storage Element
Dynamic Equality of Service in a Switch Network
Data Transfer Between Accessible Memories of Multiple Processors Incorporated in Coarse-Grained Reconfigurable (Cgr) Architecture Within Heterogeneous Processing System Using One Memory to Memory Transfer Operation
Method and Apparatus for Data Access in a Heterogeneous Processing System with Multiple Processors Using Memory Extension Operation
Method and Apparatus for Selecting Data Access Method in a Heterogeneous Processing System with Multiple Processors
Compiler for a Fracturable Data Path in a Reconfigurable Data Processor
Fracturable Data Path in a Reconfigurable Data Processor
Timing Margin Sensor
Fast Argument Load in a Reconfigurable Data Processor
Reconfigurable Data Processor with Fast Argument Load using a Runtime Program on a Host Processor
Head Of Line Blocking Mitigation In A Reconfigurable Data Processor
Two-Level Arbitration in a Reconfigurable Processor
Dynamically-Sized Data Structures on Data Flow Architectures
Logic Unit for a Reconfigurable Processor
Direct Access to Reconfigurable Processor Memory
Merging Skip-Buffers In a Reconfigurable Dataflow Processor
Buffer Splitting
Low Latency Nodes Fusion in a Reconfigurable Data Processor
High Performance Layer Normalization for Large Models
High Performance Softmax for Large Models
Defining and Executing a Section of Code for an Interpreted Software Language
Non-Uniform Memory Interleaving Processor
Flow Control for Reconfigurable Processors
Memory Unit Partitioning Solutions for Reconfigurable Dataflow Computing Systems
Peer-To-Peer Route Through in a Reconfigurable Computing System
Avoiding Use of a Subarray of Configurable Units Having a Defect
Peer-To-Peer Communication Between Reconfigurable Dataflow Units
Reconfigurable Dataflow Unit with Remote Read/Write Functionality
IC With Delay-Locked Loop With Widened Lock Range
A Scannable Memory Array and A Method for Scanning Memory
Patent:
12,243,604 →
Application:
18/752,634 →
Related Assignments
(21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 5, 2022
From: NAMA, TEJAS NAGENDRA BABU; CHAPHEKAR, RUDDHI; SIVARAMAKRISHNAN, RAM; PRABHAKAR, RAGHU
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 059509/0704 →
Assignment of Assignor's Interest
Apr 25, 2022
From: NAMA, TEJAS NAGENDRA BABU; CHAPHEKAR, RUDDHI; SIVARAMAKRISHNAN, RAM; PRABHAKAR, RAGHU
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 059697/0670 →
Assignment of Assignor's Interest
May 6, 2022
From: WANG, MINGRAN; LI, XIAOYAN; SHENG, YONGNING
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 059842/0272 →
Assignment of Assignor's Interest
Jan 4, 2023
From: ANNAMALAI, MUTHIAH
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062271/0590 →
Assignment of Assignor's Interest
Jan 4, 2023
From: ANNAMALAI, MUTHIAH
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062271/0717 →
Assignment of Assignor's Interest
Jan 4, 2023
From: ANNAMALAI, MUTHIAH
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062277/0244 →
Assignment of Assignor's Interest
Jan 25, 2023
From: POLZIN, JOSHUA; TURLIK, CONRAD ALEXANDER; GOEL, ARNAV; ZHENG, QI
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062486/0178 →
Assignment of Assignor's Interest
Jan 25, 2023
From: POLZIN, JOSHUA; TURLIK, CONRAD ALEXANDER; GOEL, ARNAV; ZHENG, QI
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062483/0529 →
Assignment of Assignor's Interest
Jan 27, 2023
From: CHEN, WEIWEI; PRABHAKAR, RAGHU; KOEPLINGER, DAVID ALAN
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062515/0216 →
Assignment of Assignor's Interest
Jan 27, 2023
From: WILSON, MARAN; TURLIK, CONRAD ALEXANDER; SABNIS, ARJUN; CHEN, YANNAN
To: PATENTS, FLAGSHIP, PATE
Reel/Frame 062504/0657 →
Assignment of Assignor's Interest
Jan 31, 2023
From: ZHANG, JIAN; GUHA, ETASH KUMAR; JIANG, TIANXIAO; DENG, ANDREW
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062547/0876 →
Assignment of Assignor's Interest
Feb 15, 2023
From: WU, PO-YU; MAZUMDAR, SUBHRA
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062704/0076 →
Assignment of Assignor's Interest
Feb 17, 2023
From: LEUNG, KIN HING; SHAH, MANISH K.; SIVARAMAKRISHNAN, RAM; PRABHAKAR, RAGHU
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062731/0987 →
Assignment of Assignor's Interest
Feb 17, 2023
From: DYKEMA, GREG; WILSON, MARAN; FENG, GUOYAO; ZHOU, KUAN
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062729/0831 →
Assignment of Assignor's Interest
Jul 3, 2023
From: SHEELEY, NATHAN FRANCIS; PRABHAKAR, RAGHU; KOEPLINGER, DAVID ALAN
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 064138/0975 →
Assignment of Assignor's Interest
Jul 4, 2023
From: VILIM, MATTHEW; PRABHAKAR, RAGHU; FELDMAN, MATT; ZHANG, YAQI
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 064143/0831 →
Assignment of Assignor's Interest
Jul 23, 2023
From: TURLIK, CONRAD ALEXANDER; WILSON, MARAN; MISRA, ANAND; VAYYALA, ANAND
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 064348/0831 →
Assignment of Assignor's Interest
Oct 9, 2023
From: NATARAJA, PRAMOD; GUPTA, SITANSHU; SIVARAMAKRISHNAN, RAM; PUNJ, AJIT
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 065156/0210 →
Assignment of Assignor's Interest
Mar 19, 2024
From: OKLOBDZIJA, VOJIN G.; KIM, MATTHEW M.
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 066827/0334 →
Assignment of Assignor's Interest
Jan 7, 2026
From: NAMA, TEJAS NAGENDRA BABU; CHAPHEKAR, RUDDHI; SIVARAMAKRISHNAN, RAM; PRABHAKAR, RAGHU
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 073381/0769 →
Assignment of Assignor's Interest
Mar 7, 2026
From: CHATTERJEE, RANEN; KUMAR, RAVINDER; SHENBAGAM, RAGHUNATH; GOEL, ARNAV
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 073998/0752 →