Granted Patent
B2
US 12,632,304 · App. 18/603,156 · Granted May 19, 2026
Computer system with reconfigurable processors
Inventors:
Raghu Prabhakar (San Jose, CA); Manish K. Shah (Austin, TX); Pramod Nataraja (San Jose, CA); David Brian Jackson (Dana Point, CA); Kin Hing Leung (Cupertino, CA); Ram Sivaramakrishnan (San Jose, CA); Sumti Jairath (Palo Alto, CA); Gregory Frederick Grohoski (Bee Cave, TX)
Assignee:
SambaNova Systems, Inc.
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Abstract
A computer system includes an array of reconfigurable processor blocks which execute fragments of a larger data processing operation. An array controller distributes a control signal to the reconfigurable processors in the array and receives control signals for the respective execution fragments. The control signal may include quiesce logic or other control methods to execute the effective execution fragments of the larger data processing operation when individual processors become available.
Claims (9)
1 . A computer system, comprising:
an array of reconfigurable processing units;
wherein the array is configured into a plurality of execution fragment resource groups (EFRGs) for executing fragments of a data processing operation, the fragments having quiesce boundaries;
wherein an execution fragment comprises, in a coarse-grained reconfigurable architecture CGRA, a subset of operations in a control and data flow graph of the data processing operation; and
a quiesce controller for distributing quiesce control signals to quiesce logic associated with the reconfigurable processing units in the array, and for receiving quiesce ready signals from the plurality of execution fragment resource groups EFRGs,
wherein the quiesce boundaries use configuration data defining sets of configured states of execution in the reconfigurable processing units configured to execute the execution fragments.
2 . The system of claim 1 , further configured to generate the control signal in response to an internal event originating in the array.
3 . The system of claim 1 , further configured to generate the control signal in response to an external event originating outside the array.
4 . The system of claim 1 , wherein the control signal is asynchronous relative to the execution fragments.
Assignments (3)
INTELLECTUAL PROPERTY SECURITY AGREEMENT
Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Apr 4, 2025
From: PRABHAKAR, RAGHU; SHAH, MANISH K.; NATARAJA, PRAMOD; JACKSON, DAVID BRIAN; LEUNG, KIN HING; SIVARAMAKRISHNAN, RAM; JAIRATH, SUMTI; GROHOSKI, GREGORY FREDERICK
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 070728/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Nov 13, 2024
From: PRABHAKAR, RAGHU; SHAH, MANISH K.; NATARAJA, PRAMOD; JACKSON, DAVID BRIAN; LEUNG, KIN HING; SIVARAMAKRISHNAN, RAM; JAIRATH, SUMTI; GROHOSKI, GREGORY FREDERICK
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 069233/0176 →
Continuity (3)
References Cited (108)
US 4769790A
· Yamashita
· 1988
[cited by applicant]
US 4884197A
· Sachs
· 1989
[cited by examiner]
US 5560029A
· Papadopoulos et al.
· 1996
[cited by applicant]
US 5963746A
· Barker et al.
· 1999
[cited by applicant]
US 6105119A
· Kerr et al.
· 2000
[cited by applicant]
US 6119181A
· Vorbach et al.
· 2000
[cited by applicant]
US 6728871B1
· Vorbach et al.
· 2004
[cited by applicant]
US 7117391B1
· Hornick
· 2006
[cited by examiner]
US 7797258B1
· Bowman et al.
· 2010
[cited by applicant]
US 20040049672A1
· Nollet et al.
· 2004
[cited by applicant]
US 20060190517A1
· Guerrero
· 2006
[cited by applicant]
US 20110264723A1
· Yagain
· 2011
[cited by applicant]
US 20130227255A1
· Kim
· 2013
[cited by applicant]
US 20140149480A1
· Catanzaro et al.
· 2014
[cited by applicant]
US 20140317628A1
· Kim
· 2014
[cited by applicant]
US 20140331031A1
· Suh et al.
· 2014
[cited by applicant]
US 20170083313A1
· Sankaralingam et al.
· 2017
[cited by applicant]
US 20190303297A1
· Fleming, Jr. et al.
· 2019
[cited by applicant]
CN 1122026A
· 1996
[cited by applicant]
CN 103748574B
· 2016
[cited by applicant]
EP 0733234A
· 1995
[cited by applicant]
EP 1372084A2
· 2003
[cited by applicant]
TW 200801964A
· 2008
[cited by applicant]
TW 200928736A
· 2009
[cited by applicant]
TW I758770B
· 2022
[cited by applicant]
WO 2021007131A1
· 2021
[cited by applicant]
Prabhakar, Raghu, et al. “Plasticine: A reconfigurable architecture for parallel paterns.” ACM SIGARCH Computer Architecture News 45.2 (2017): 389-402. (Year: 2017).
[cited by examiner]
80.192.25.230: “Producer-consumer problem”, Feb. 7, 2013 {Feb. 7, 2013), XP055530821, Retrieved from the ntemet: URL:https://en.wikipedia.org/w/index.php?t>ille=Producer″/oE2%80%93consumer_problem&old d=537111527 [retri…
[cited by applicant]
AMBA AXI and ACE Protocol Specification, ARM, as early as Jan. 2003, 440 pages.
[cited by applicant]
Ando et al., “A Multithreaded CGRA for Convolutional Neural Network Processing,” Scientific Research Publishing, Circuits and Systems, Jun. 2017, pp. 149-170.
[cited by applicant]
Anonymous, Activation Function, Wikipedia, Retrieved on Aug. 16, 2019, 3 pages. Retrieved from [ URL: https://en.wikipedia.org/wiki/Activation_function ].
[cited by applicant]
Basterretxea et al., “Approximation of sigmoid function and the derivative for hardware implementation of artificial neurons,” IEE Proceedings—Circuits, Devices and Systems, vol. 151, Issue 1, Feb. 5, 2004, 7 pages.
[cited by applicant]
Benoit et al., Automatic Task Scheduling/ Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures, Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE Internat…
[cited by applicant]
De Sutter et al., Coarse-Grained Reconfigurable Array Architectures, 2010 Handbook of Signal Processing Systems, 37 pages.
[cited by applicant]
Eppler et al., High speed neural network chip for trigger purposes in high energy physics, IEEE, Proc. of the conference on design, automation and test in Europe, Feb. 1998, 8 pages.
[cited by applicant]
Fiolhais et al., “Overlay Architectures for Space Applications,” SpacE FPGA Users Workshop, Apr. 9-11, 2018, pp. 1-20.
[cited by applicant]
Gomar et al. “Precise digital implementations of hyperbolic tanh and sigmoid function,” 2016 50th Asilomar Conference on Signals, Systems and Computers, Nov. 6-9, 2016, 4 pages.
[cited by applicant]
Harris et al., Architectures and Algorithms for User Customization of CNNs, ASP-DAC 2018, 32 pages.
[cited by applicant]
Hartenstein, Coarse Grain Reconfigurable Architectures, IEEE, 2001, 6 pages.
[cited by applicant]
Iannucci, “Toward a dataflow/von Neumann hybrid architecture,” ISCA '88 Proc. of the 15th Annual ISCA, May 30-Jun. 2, 1988, 10 pages.
[cited by applicant]
Jafri et al., NeuroCGRA: A CGRAs with Support for Neural Networks, 2014 International Conference on High Performance Computing & Simulation (HPCS), 8 pages.
[cited by applicant]
Koeplinger et al., Spatial: A Language and Compiler for Application Accelerators, PLDI '18, Jun. 18-22, 2018, Association for Computng Machinery, 16 pages.
[cited by applicant]
Li, et al., “Caterpillar: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks,” arXiv: 1706.00517v2 [cs.DC], Jun. 8, 2017, 10 pages.
[cited by applicant]
Lin et al., “A Digital Circuit Design of Hyperbolic Tangent Sigmoid Function for Neural Networks,” 2018 IEEE Int'l Symp. on Circuits and Systems, May 18-21, 2018, 4 pages.
[cited by applicant]
Nicol, “A Course Grain Reconfigurable Array (CGRA) for Statically Scheduled Data Flow Computing,” Wave Computing, May 3, 2017, 9 pages.
[cited by applicant]
Nicol, “Wave Computing: A Dataflow Processing Chip for Training Deep Neural Networks,” 2017, 25 pages.
[cited by applicant]
Paek et al., “Binary Acceleration Using Coarse-Grained Reconfigurable Architecture,” ACM SIGARCH Computer Architecture News, vol. 38, No. 4, Sep. 2010, 7 pages.
[cited by applicant]
PCT/US2019/062287—International Search Report and Written Opinion dated Feb. 5, 2020, 18 pages.
[cited by applicant]
PCT/US2019/062289—International Search Report and Written Opinion dated Feb. 28, 2020, 14 pages.
[cited by applicant]
PCT/US2020/012079—International Search Report and Written Opinion mailed Apr. 29, 2020, 18 pages.
[cited by applicant]
PCT/US2020/014652—International Search Report and Written Opinion dated May 26, 2020, 9.
[cited by applicant]
PCT/US2020/032186—International Search Report and Written Opinion dated Aug. 14, 2020; 21 pages.
[cited by applicant]
PCT/US2020/040832—International Search Report and the Written Opinion dated Sep. 18, 2020, 18 pages.
[cited by applicant]
PCT/US2020/040832—International Preliminary Report on Patentability, dt. Jan. 20, 2022, 16 pages.
[cited by applicant]
Prabhakar et al., Plasticine: A Reconfigurable Architecture for Parallel Patterns, ISCA, Jun. 24-28, 2017, 14 pages.
[cited by applicant]
Tanomoto et al., “A CGRA-based Approach for Accelerating Convolutional Neural Networks,” 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015, pp. 73-80.
[cited by applicant]
Tobuschat, et al., “IDAMC: a NoC for mixed criticality systems,” 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, Taipei, Aug. 19-21, 2013, pp. 149-156.
[cited by applicant]
Turkson et al. “Artificial neural network applications in the calibration of spark-ignition engines: An overview,” Engineering Science and Technology, an International Journal, vol. 19, Issue 3, Sep. 2016, 1346-1359.
[cited by applicant]
TW 109102852—Office Action dated Jan. 30, 2020, 6 pages.
[cited by applicant]
TW110101760—Notice of Allowance, dated Sep. 21, 2022, 2 pages.
[cited by applicant]
U.S. Appl. No. 16/239,252—Office Action dated Aug. 7, 2019, 8 pages.
[cited by applicant]
U.S. Appl. No. 16/260,548—Office Action, dated Dec. 26, 2019, 9 pages.
[cited by applicant]
U.S. Appl. No. 16/407,675—Office Action, dated May 18, 2020, 9 pages.
[cited by applicant]
U.S. Appl. No. 16/407,675—Office Action, dated Oct. 29, 2020, 7 pages.
[cited by applicant]
U.S. Appl. No. 16/862,445—Office Action dated Mar. 18, 2021, 25 pages.
[cited by applicant]
U.S. Appl. No. 17/322,697—Non-Final Office Action, dated Apr. 7, 2023, 19 pages.
[cited by applicant]