Multiple test modes for a memory in an integrated circuit
An integrated circuit (IC) includes a memory array with M rows of N storage elements that has an N-bit wide parallel input and output, and a 1-bit wide array scan input and output. A memory built-in self-test (MBIST) circuit is connected to the memory array to generate test addresses and N-bit wide test data. Functional circuitry with a functional address bus and N-bit wide functional data path is linked to the memory array. Control circuitry enables a serial test mode for shifting data through the storage elements, a MBIST mode for test data access, and a normal operation mode for functional data access. This IC design offers versatile memory testing and operational capabilities.
1 . An integrated circuit (IC) comprising:
a memory array comprising M rows of N storage elements each and having an N-bit wide parallel input, an N-bit wide parallel output, a 1-bit wide array scan input, and a 1-bit wide array scan output, wherein N and M are positive integers greater than 1;
a memory built-in self-test (MBIST) circuit coupled to the memory array to generate test addresses and N-bit wide test data;
functional circuitry coupled to the memory array and comprising a functional address bus and an N-bit wide functional data path;
control circuitry, coupled to the memory array, to provide:
a serial test mode for the memory array that serially shifts data from the 1-bit wide array scan input through every storage element at least one row of the M rows of N storage elements of the memory array and out of the 1-bit wide array scan output,
a MBIST mode for the memory array that uses the test addresses to provide N-bit wide access for writes of the N-bit wide test data to the memory array and N-bit wide reads of the memory array for data verification, and
a normal operation mode for the memory array that uses the functional address bus to provide N-bit wide access for the functional data path to read from and write to the memory array; and
the memory array further comprising:
an input clock;
a N-bit wide input buffer, coupled to the storage elements, and enabled to load data during a first part of a clock period of the input clock;
an output multiplexer, coupled to the storage elements, enabled to output data from a chosen row of the M rows of storage elements in parallel on a N-bit wide output data path under control of the control circuitry; and
an input multiplexer, coupled to the input buffer, the functional data path, the MBIST circuit, the array scan input, and a subset of lines of the N-bit wide output data path, and enabled to select, as an input to the input buffer, between a first input coupled to the functional data path, a second input coupled to the MBIST circuit, and a third input coupled to a set of inputs including the array scan input and the subset of lines of the N-bit wide output data path, under control of the control circuitry,
wherein the storage elements are enabled to load data from the input buffer to a selected row of the M rows storage elements in parallel during a second part of the clock period of the input clock under control of the control circuitry,
wherein the N-bit wide output data path and the third input of the input multiplexor each have N lines, numbered from N−1 to 0,
wherein the 1-bit wide array scan input is coupled to line N−1 of the third input of the input multiplexer,
wherein lines N−1 through 1 of the N-bit wide output data path are respectively coupled to lines N−2 through 0 of the third input of the input multiplexer, and
wherein the 1-bit wide array scan output is coupled to line 0 of the N-bit wide output data path.
2 . The IC of claim 1 , the control circuitry comprising a counter that is incremented using the input clock while in the serial test mode, wherein an upper portion of the counter is used to select one of the M rows of storage elements during the serial test mode, and wherein data is serially shifted through every storage element of the M rows of N storage elements in the serial test mode.
3 . The IC of claim 1 , wherein the first part of the clock period is between a falling edge and a rising edge of the input clock and the second part of the clock period is between a rising edge and a falling edge of the input clock.
4 . The IC of claim 1 , wherein the storage elements in the M rows of N storage elements respectively comprise a single transparent latch and the N-bit wide input buffer comprises N transparent latches.
5 . A method of testing a memory array in an integrated circuit (IC), the memory array including M rows of N storage elements each and having an N-bit wide parallel input, an N-bit wide parallel output, a 1-bit wide array scan input, and a 1-bit wide array scan output, wherein N and M are positive integers greater than 1, the method comprising:
setting a serial test mode and serially shifting first test data into a 1-bit wide array scan input through every storage element of at least one row of the M rows of N storage elements of the memory array and out of the 1-bit wide array scan output;
setting a memory built-in self-test (MBIST) mode and using a MBIST circuit of the IC to generate test addresses and N-bit wide second test data and using the test addresses to provide N-bit wide access for writes of the N-bit wide second test data to the memory array and N-bit wide reads of the memory array for data verification;
setting a normal operation mode and using functional circuitry of the IC for N-bit wide reads and writes of the memory array;
choosing output data from a chosen row of the M rows of storage elements to output in parallel on a N-bit wide output data path;
selecting N-bit wide input data from either a first input coupled to a functional data path, a second input coupled to the MBIST circuit, or a third input coupled to the 1-bit wide array scan input and an upper N−1 lines of the N-bit wide output data path;
loading the selected N-bit wide input data into an N-bit wide input buffer during a first part of a clock period of an input clock; and
storing the N-bit wide data loaded into the input buffer in a selected row of the M rows of storage elements in parallel during a second part of the clock period of the input clock,
wherein the 1-bit wide array scan input is coupled a most significant bit of the third input, a most significant N−1 lines of the N-bit wide output data path are respectively coupled to a least significant N−1 lines of the third input, and the 1-bit wide array scan output is coupled to a least significant line of the N-bit wide output data path.
6 . The method of claim 5 , further comprising: using a counter output during the serial test mode to both choose the chosen row and select the selected row; using the test addresses during the MBIST mode to both choose the chosen row and select the selected row; and using a functional address from the functional circuitry during the normal operation mode to choose the chosen row for a read of the memory array and to select the selected row for a write to the memory array.
7 . The method of claim 6 , further comprising incrementing the counter using the input clock during the serial test mode and using a most significant portion of the counter output to both choose the chosen row and select the selected row.
8 . The method of claim 5 , further comprising serially shifting the first test data through every storage element of the M rows of N storage elements of the memory array during the serial test mode.