DATAFLOW ARCHITECTURE PROCESSOR STATICALLY RECONFIGURABLE TO PERFORM N-DIMENSIONAL AFFINE TRANSFORMATION IN A TILED MANNER

1 . A statically reconfigurable dataflow architecture processor (SRDAP) to perform an N-dimensional affine transform specified by a matrix on an N-dimensional input image to produce an N-dimensional output image comprising output pixels, each output pixel having a coordinate in each of the N dimensions, wherein N is at least two, comprising:

N counters statically reconfigurable to iterate over the output image by N respective stride values to generate base pixel coordinates of N-dimensional output tiles into which the output image is subdividable, wherein the N stride values are N output tile dimension lengths of the output tiles;

one or more pattern compute units (PCUs) statically reconfigurable to, for each output tile of the output tiles:

use the base pixel coordinates of the output tile and the N output tile dimension lengths to calculate the coordinates of corner pixels of the output tile; and

apply the affine transform matrix to coordinates of corner pixels of the output tile and use results thereof to determine coordinates of a base pixel of a corresponding N-dimensional input tile into which the input image is subdividable; and

one or more pattern memory units (PMUs) statically reconfigurable to be loaded with each corresponding input tile based on the determined coordinates of the base pixel of the input tile.

2 . The SRDAP of claim 1 , further comprising:

configuration stores loadable with configuration data to statically reconfigure the SRDAP.

3 . The SRDAP of claim 2 ,

wherein to statically reconfigure the SRDAP comprises loading the configuration stores with the configuration data prior to initiation of production of the output image without re-loading the configuration stores with the configuration data until completion of production of the output image.

4 . The SRDAP of claim 1 ,

wherein the one or more PCUs comprise counters statically reconfigurable to, for each output tile of the output tiles, and for all the output pixels of the output tile:

iterate over the output tile to generate vectors of coordinates that are local to the output tile of the output pixels; and

calculate vectors of coordinates that are global to the output image of the output pixels as a sum of the vectors of local output pixel coordinates and the output tile base pixel coordinates.

5 . The SRDAP of claim 4 ,

wherein the one or more PCUs are further statically reconfigurable to, for each output tile and the corresponding input tile, and for all the output pixels of the output tile:

apply the affine transform matrix to the vectors of global output pixel coordinates to calculate vectors of coordinates global to the input image of input pixels of the corresponding input tile; and

subtract the input tile base pixel coordinates from the vectors of global input pixel coordinates to calculate vectors of coordinates that are local to the input tile of the input pixels.

6 . The SRDAP of claim 5 ,

wherein the one or more PCUs are further statically reconfigurable to, for each output tile and the corresponding input tile, and for all the output pixels of the output tile:

calculate, using the vectors of local input pixel coordinates and inner N−1 input tile dimension lengths of the input tiles, vectors of PMU addresses of the input pixels.

7 . The SRDAP of claim 6 ,

wherein the one or more PMUs are further statically reconfigurable to:

read values of the input pixels at the calculated vectors of PMU addresses; and

write vectors of the input pixel values to one or more PMUs to form the output tile.

8 . The SRDAP of claim 6 ,

wherein the input tile dimension lengths are determinable a priori and statically reconfigurable in the SRDAP for use in loading the input tiles from a host memory external to the SRDAP.

9 . The SRDAP of claim 4 ,

wherein each of the PCUs comprises a vector of pipelines, each pipeline comprising:

a counter, associated with an inner dimension of the N dimensions, of the counters statically reconfigurable to iterate over the output tile; and

wherein the counter of each pipeline counts autonomously during performance of the N-dimensional affine transform with respect to each output tile without incurring processing overhead associated with scheduling execution of instructions due to implicit instruction operand dependencies.

10 . The SRDAP of claim 1 ,

wherein each of the N counters is statically reconfigurable with a maximum count value; and

wherein a counter of the N counters corresponding to a next-to-outermost dimension of the N dimensions is statically reconfigurable to signal to load a next input tile of the input tiles upon having counted to the maximum value.

11 . The SRDAP of claim 1 ,

wherein the static reconfigurability of the SRDAP enables the SRDAP to perform the N-dimensional affine transform without incurring processing overhead associated with fetching instructions.

12 . A computer-implemented method for performing an N-dimensional affine transform specified by a matrix on an N-dimensional input image to produce an N-dimensional output image comprising output pixels, each output pixel having a coordinate in each of the N dimensions, wherein N is at least two, comprising:

statically reconfiguring a statically reconfigurable dataflow architecture processor (SRDAP) that comprises N counters, one or more pattern compute units (PCUs), and one or more pattern memory units (PMUs);

iterating, by the N counters, over the output image by N respective stride values to generate base pixel coordinates of N-dimensional output tiles into which the output image is subdividable, wherein the N stride values are N output tile dimension lengths of the output tiles;

by the one or more pattern compute units (PCUs), for each output tile of the output tiles:

using the base pixel coordinates of the output tile and the N output tile dimension lengths to calculate the coordinates of corner pixels of the output tile; and

applying the affine transform matrix to coordinates of corner pixels of the output tile and using results thereof to determine coordinates of a base pixel of a corresponding N-dimensional input tile into which the input image is subdividable; and

loading the one or more pattern memory units (PMUs) with each corresponding input tile based on the determined coordinates of the base pixel of the input tile.

13 . The method of claim 12 , further comprising:

wherein said statically reconfiguring the SRDAP comprises loading configuration stores of the SRDAP with configuration data.

14 . The method of claim 13 ,

wherein said statically reconfiguring the SRDAP comprises loading the configuration stores with the configuration data prior to initiation of production of the output image without re-loading the configuration stores with the configuration data until completion of production of the output image.

15 . The method of claim 12 , further comprising:

by counters of the one or more PCUs, for each output tile of the output tiles, and for all the output pixels of the output tile:

iterating over the output tile to generate vectors of coordinates that are local to the output tile of the output pixels; and

calculating vectors of coordinates that are global to the output image of the output pixels as a sum of the vectors of local output pixel coordinates and the output tile base pixel coordinates.

16 . The method of claim 15 , further comprising:

by the one or more PCUs, for each output tile and the corresponding input tile, and for all the output pixels of the output tile:

applying the affine transform matrix to the vectors of global output pixel coordinates to calculate vectors of coordinates global to the input image of input pixels of the corresponding input tile; and

subtracting the input tile base pixel coordinates from the vectors of global input pixel coordinates to calculate vectors of coordinates that are local to the input tile of the input pixels.

17 . The method of claim 16 , further comprising:

by the one or more PCUs, for each output tile and the corresponding input tile, and for all the output pixels of the output tile:

calculating, using the vectors of local input pixel coordinates and inner N−1 input tile dimension lengths of the input tiles, vectors of PMU addresses of the input pixels.

18 . The method of claim 17 , further comprising:

by the one or more PMUs:

reading values of the input pixels at the calculated vectors of PMU addresses; and

writing vectors of the input pixel values to one or more PMUs to form the output tile.

19 . The method of claim 17 , further comprising:

wherein the input tile dimension lengths are determinable a priori; and

statically reconfiguring the input tile dimension lengths in the SRDAP for use in loading the input tiles from a host memory external to the SRDAP.

20 . A non-transitory computer-readable storage medium having computer program instructions stored thereon that are capable of causing or configuring a statically reconfigurable dataflow architecture processor (SRDAP) to perform an N-dimensional affine transform specified by a matrix on an N-dimensional input image to produce an N-dimensional output image comprising output pixels, each output pixel having a coordinate in each of the N dimensions, wherein N is at least two, comprising:

N counters statically reconfigurable to iterate over the output image by N respective stride values to generate base pixel coordinates of N-dimensional output tiles into which the output image is subdividable, wherein the N stride values are N output tile dimension lengths of the output tiles;

one or more pattern compute units (PCUs) statically reconfigurable to, for each output tile of the output tiles:

use the base pixel coordinates of the output tile and the N output tile dimension lengths to calculate the coordinates of corner pixels of the output tile; and

apply the affine transform matrix to coordinates of corner pixels of the output tile and use results thereof to determine coordinates of a base pixel of a corresponding N-dimensional input tile into which the input image is subdividable; and

one or more pattern memory units (PMUs) statically reconfigurable to be loaded with each corresponding input tile based on the determined coordinates of the base pixel of the input tile.