Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations
A heterogeneous processing system and method including a host processor with a host memory having allocated buffer space, first and second processors each with memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the processors and the transfer resources. The first processor executes a first part of an application generating first data stored into the first memory. A data transfer resource is programed to transfer the first data to the buffer space and to transfer the first data from the buffer space into the second memory. The second processor executes a second part of the application generating second data stored into the second memory. The data transfer resources may include a DMA engine in which the buffer space is DMA addressable. One of the first and second processors may be a reconfigurable processor, a compute engine, or a reconfigurable dataflow unit.
1. A heterogeneous processing system, comprising:
switch and bus circuitry;
a host processor coupled to a host memory accessible from the host processor without utilizing the switch and bus circuitry, wherein the host processor allocates buffer space within the host memory;
a first processor coupled to a first memory accessible from the first processor without utilizing the switch and bus circuitry;
a second processor coupled to a second memory accessible from the second processor without utilizing the switch and bus circuitry;
a first direct memory access (DMA) engine incorporated within the first processor; and
a second DMA engine incorporated within the second processor;
wherein the switch and bus circuitry communicatively couples the host processor, the host memory, the first DMA engine of the first processor and the second DMA engine of the second processor;
wherein the first processor is configured to execute a first node of a computation graph which creates and stores first data into the first memory without using the switch and bus circuitry; and
wherein the host processor is configured to program the first DMA engine to transfer the first data from the first memory to a first location in the buffer space of the host memory through the switch and bus circuitry and to program the first DMA engine to transfer the first data from the first location in the buffer space of the host memory into the second memory through the switch and bus circuitry.
2. The heterogeneous processing system of claim 1 , wherein the buffer space comprises a common buffer that is allocated within the host memory as a pinned memory buffer.
3. The heterogeneous processing system of claim 1 , wherein the buffer space comprises a common buffer that is allocated within a non-swappable portion of the host memory.
4. The heterogeneous processing system of claim 1 , wherein at least one of the first and second processors comprises a reconfigurable processor or a reconfigurable dataflow unit that is configured by the host processor.
5. The heterogeneous processing system of claim 1 , wherein the host processor is configured to prompt the first DMA engine to transfer the first data from the buffer space of the host memory into the second memory, and wherein the second processor comprises a compute engine that is configured by the host processor to execute a second node of the computation graph using the first data to generate and store second data into the second memory.
6. The heterogeneous processing system of claim 1 , wherein the host processor is configured to prompt the first DMA engine after the first data is stored into the first memory to transfer the first data from the first memory into the buffer space of the host memory, and to prompt the second DMA engine after the first data is stored in the buffer space to transfer the first data from the buffer space to the second memory.
7. The heterogeneous processing system of claim 1 , wherein the host processor is configured to dynamically program the first DMA engine to transfer the first data from the first memory to the buffer space of the host memory during operation of the computation graph.
8. A method of transferring data in a heterogeneous system, wherein the heterogeneous system includes switch and bus circuitry, a host processor coupled to a host memory accessible from the host processor without utilizing the switch and bus circuitry, a first processor coupled to a first memory accessible from the first processor without utilizing the switch and bus circuitry, a second processor coupled to a second memory accessible from the second processor without utilizing the switch and bus circuitry, a first direct memory access (DMA) engine incorporated within the first processor, a second DMA engine incorporated within the second processor, wherein the switch and bus circuitry communicatively couples the host processor, the host memory, the first DMA engine of the first processor, and the second DMA engine of the second processor, the method comprising:
allocating buffer space in the host memory;
programming the first DMA engine with a first source address in the first memory and a first address in the buffer space;
programming the second DMA engine with the first address in the buffer space and a second destination address in the second memory;
executing a first node of a computation graph by the first processor which creates and stores first data into the first memory without using the switch and bus circuitry;
causing the first DMA engine to transfer the first data from the first memory through the switch and bus circuitry to the buffer space starting at the first address in the host memory; and
causing the second DMA engine to transfer the first data from the buffer space starting at the first address in the host memory through the switch and bus circuitry to the second memory.
9. The method of claim 8 , wherein the allocating buffer space comprises allocating a common buffer as a pinned memory buffer.
10. The method of claim 8 , wherein the allocating buffer space comprises allocating a common buffer within a non-swappable portion of the host memory.
11. The method of claim 8 , wherein at least one of the first and second processors comprises a reconfigurable processor, further comprising configuring, by the host processor, the reconfigurable processor to execute at least one node of the computation graph.
12. The method of claim 8 , wherein at least one of the first and second processors comprises a reconfigurable dataflow unit, further comprising configuring, by the host processor, the reconfigurable dataflow unit to execute at least one node of the computation graph.
13. The method of claim 8 , further comprising executing a second node of the computation graph by the second processor which uses the first data to generate second data and stores the second data into the second memory.
14. The method of claim 8 , wherein the first processor comprises a compute engine, further comprising configuring the compute engine by the host processor to execute the first node of the computation graph to create the first data and to store the first data into the first memory.
15. The method of claim 8 , wherein the second processor comprises a compute engine, the method further comprising configuring, by the host processor, the compute engine to execute a second node of the computation graph using the first data to generate second data and to store the second data into the second memory.
16. The method of claim 8 , further comprising prompting the first DMA engine after the first data is stored into the first memory to transfer the first data from the first memory to the buffer space, and prompting the second DMA engine after the first data is stored in the buffer space of the host memory to transfer the first data from the buffer space to the second memory.
17. The method of claim 8 , further comprising dynamically programming the first DMA engine with the first source address in the first memory and the first address in the buffer space during operation of the computation graph.
18. The method of claim 8 , further comprising dynamically programming the second DMA engine with the first address in the buffer space and the second destination address in the second memory during operation of the computation graph.