IP Library Granted Patent US 11,182,264
Granted Patent B1
US 11,182,264 · App. 17/127,818 · Granted Nov 23, 2021

Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Inventors: Ram Sivaramakrishnan (San Jose, CA); Sumti Jairath (Santa Clara, CA); Emre Ali Burhan (Sunnyvale, CA); Manish K. Shah (Austin, TX); Raghu Prabhakar (San Jose, CA); Ravinder Kumar (Fremont, CA); Arnav Goel (San Jose, CA); Ranen Chatterjee (Fremont, CA); Gregory Frederick Grohoski (Bee Cave, TX); Kin Hing Leung (Cupertino, CA); Dawei Huang (San Diego, CA); Manoj Unnikrishnan (Saratoga, CA); Martin Russell Raumann (San Leandro, CA); Bandish B. Shah (San Francisco, CA)
Assignee: SambaNova Systems, Inc.
G06F11/26G06F9/547G06F11/2236G06F11/2268G06F15/7871
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Quick Facts
Patent No.
US 11,182,264
App. No.
17/127,818
Granted
Nov 23, 2021
Kind
B1
Abstract

A data processing system comprises a plurality of reconfigurable processors including a first reconfigurable processor and additional reconfigurable processors, a plurality of buffers in a shared memory accessible to the first reconfigurable processor and the additional reconfigurable processors, and runtime logic configured to execute one or more configuration files for applications using the first reconfigurable processor and the additional reconfigurable processors. Execution of the configuration files includes receiving data from the first reconfigurable processor and providing the data to at least one of the additional reconfigurable processors, and receiving data from the at least one of the additional reconfigurable processors and providing the data to the first reconfigurable processor.

Claims (34)

1. A data processing system, comprising:

a plurality of reconfigurable processors, reconfigurable processors in the plurality of reconfigurable processors having reconfigurable processor memory;

a plurality of host processors, a host processor in the plurality of host processors operatively coupled to the reconfigurable processors and having host memory;

a plurality of buffers, the buffers in the plurality of buffers including reconfigurable processors-to-host processor buffers configured to receive data from the reconfigurable processors and provide the data to the host processor, and host processor-to-reconfigurable processors buffers configured to receive data from the host processor and provide the data to the reconfigurable processors;

wherein the host processor, the reconfigurable processors, and the plurality of buffers are connected via one or more local buses;

runtime logic, running on the host processor, configured to load and execute one or more configuration files for applications on the reconfigurable processors using at least one of the host processor-to-reconfigurable processors buffers and via at least one of the local buses that connects the host processor, the reconfigurable processors, and the at least one of the host processor-to-reconfigurable processors buffers, thereby configuring the reconfigurable processors to execute the applications; and

the reconfigurable processors configured to process the configuration files and data for the applications and generate outputs, and to send the outputs to the host processor using at least one of the reconfigurable processors-to-host processor buffers and via at least one of the local buses that connects the host processor, the reconfigurable processors, and the at least one of the reconfigurable processors-to-host processor buffers.

2. The data processing system of claim 1 , wherein a debugging logic is configured to detect and report errors to a debugging console on the host processor based on comparison of the outputs to expected outputs.

3. The data processing system of claim 2 , wherein the debugging logic is further configured to report the errors to a debug output file on the host processor based on the comparison.

4. The data processing system of claim 1 , wherein the buffers are accessible to the reconfigurable processors and the host processor.

5. The data processing system of claim 4 , wherein the buffers are in the reconfigurable processor memory, and the reconfigurable processor memory is accessible to the host processor.

6. The data processing system of claim 4 , wherein the buffers are in the host memory, and the host memory is accessible to the reconfigurable processors and the host processor.

7. The data processing system of claim 4 , wherein the buffers are in a Network Interface Controller (NIC) that is accessible to the reconfigurable processors and the host processor.

8. The data processing system of claim 1 , wherein the buffers are First-In, First-Out (FIFO) buffers.

9. The data processing system of claim 1 , wherein the reconfigurable processors notify the host processor of error reporting using one or more remote procedure calls.

10. The data processing system of claim 9 , wherein the reconfigurable processors use at least one of the reconfigurable processors-to-host processor buffers to send one or more argument values to the host processor for execution of the remote procedure calls.

11. The data processing system of claim 1 , wherein the runtime logic is further configured to execute one or more test configuration files for test applications on the reconfigurable processors, wherein the reconfigurable processors are further configured to process the test configuration files and data for the test applications and generate test outputs, and to send the test outputs to the host processor using at least one of the reconfigurable processors-to-host processor buffers, and wherein testing logic, running on the host processor, is configured to determine test statistics based on the test outputs, and to report the test statistics to a test output file on the host processor.

12. A data processing system, comprising:

a plurality of reconfigurable processors, reconfigurable processors in the plurality of reconfigurable processors having reconfigurable processor memory;

a plurality of host processors, a host processor in the plurality of host processors operatively coupled to the reconfigurable processors and having host memory;

a plurality of buffers, the buffers in the plurality of buffers including reconfigurable processors-to-host processor buffers configured to receive data from the reconfigurable processors and provide the data to the host processor, and host processor-to-reconfigurable processors buffers configured to receive data from the host processor and provide the data to the reconfigurable processors;

wherein the host processor, the reconfigurable processors, and the plurality of buffers are connected via one or more local buses;

runtime logic configured to load one or more configuration files for applications on the reconfigurable processors for execution using at least one of the host processor-to-reconfigurable processors buffers and via at least one of the local buses that connects the host processor, the reconfigurable processors, and the at least one of the host processor-to-reconfigurable processors buffers, thereby configuring the reconfigurable processors to execute the applications, the configuration files including a plurality of functions; and

the runtime logic configured to execute a first set of functions in the plurality of functions and data therefor on the reconfigurable processors, and a second set of functions in the plurality of functions and data therefor on the host processor,

wherein functions in the second set of functions and the data therefor are transmitted to the host processor using one or more of the reconfigurable processors-to-host processor buffers and via at least one of the local buses that connects the host processor, the reconfigurable processors, and the one or more of the reconfigurable processors-to-host processor buffers, and

wherein results of executing the functions and/or and the data therefor on the host processor are transmitted to the reconfigurable processors using one or more of the host processor-to-reconfigurable processors buffers and via at least one of the local buses that connects the host processor, the reconfigurable processors, and the one or more of the host processor-to-reconfigurable processors buffers.

13. The data processing system of claim 12 , wherein the data on which for the first and second sets of functions are transmitted to the host processor using the one or more of the reconfigurable processors-to-host processor buffers.

14. The data processing system of claim 12 , further comprising using respective ones of the reconfigurable processors-to-host processor buffers to transmit respective functions in the second set of functions and data therefor to the host processor.

15. The data processing system of claim 14 , further comprising using respective ones of the host processor-to-reconfigurable processors buffers to transmit results of executing the respective functions.

16. The data processing system of claim 12 , wherein the buffers are accessible to the reconfigurable processors and the host processor.

17. The data processing system of claim 16 , wherein the buffers are in the reconfigurable processor memory, and the reconfigurable processor memory is accessible to the host processor.

18. The data processing system of claim 16 , wherein the buffers are in the host memory, and the host memory is accessible to the reconfigurable processors and the host processor.

19. The data processing system of claim 16 , wherein the buffers are in a Network Interface Controller (NIC) that is accessible to the reconfigurable processors and the host processor.

20. The data processing system of claim 16 , wherein the buffers are First-In, First-Out (FIFO) buffers.

Assignments (3)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 057530 FRAME 0477. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded Oct 2, 2021
From: SIVARAMAKRISHNAN, RAM; JAIRATH, SUMTI; BURHAN, EMRE ALI; SHAH, MANISH K.; PRABHAKAR, RAGHU; KUMAR, RAVINDER; GOEL, ARNAV; CHATTERJEE, RANEN; GROHOSKI, GREGORY FREDERICK; LEUNG, KIN HING; HUANG, DAWEI; UNNIKRISHNAN, MANOJ; RAUMANN, MARTIN RUSSELL; SHAH, BANDISH B.
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 057689/0018 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2021
From: SIVARAMAKRISHNAN, RAM; JAIRATH, SUMTI; BURHAN, EMRE ALI; SHAH, MANISH K.; PRABHAKAR, RAGHU; KUMAR, RAVINDER; GOEL, ARNAV; CHATTERJEE, RANEN; GROHOSKI, GREGORY FREDERICK; LEUNG, KIN HING; HUANG, DAWEI; UNNIKRISHNAN, MANOJ; RAUMANN, MARTIN RUSSELL; SHAH, BANDISH B.
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 057530/0477 →
Cited By (10)
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