Bandwidth-aware computational graph mapping
A computer-implemented method of transforming a high-level program for mapping onto a coarse-grained reconfigurable (CGR) processor with an array of CGR units, including sectioning a dataflow graph into a plurality of sections; extracting performance information for each of the plurality of sections; on a CGR unit: assigning to a section at least two computations dependent on a first data element; scheduling an additional load of the first data element in response to available memory bandwidth for that section; eliminating a buffer between the additional load of the first data element and one of the two computations, for that section; generating configuration data for the placed positions and the routed data and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and storing the configuration data in a non-transitory computer-readable storage medium.
1. A computer-implemented method of transforming a high-level program into configuration data executable by a coarse-grained reconfigurable (CGR) processor including one or more arrays of CGR units, comprising:
sectioning a dataflow graph of the high-level program into a plurality of sections to be mapped to the one or more arrays of CGR units of the CGR processor;
extracting performance information for each of the plurality of sections;
assigning a section of the plurality of sections that includes at least two computations dependent on a first data element to one or more CGR units of the CGR processor, wherein the first data element is loaded from a memory;
scheduling an additional load of the first data element from the memory based at least in part on the performance information for the section indicating available memory bandwidth for the section;
eliminating from the section, a buffer between a load of the first data element from the memory and one of the two computations dependent on the first data element;
generating the configuration data for the CGR processor including placed positions, data routing, and communication channels, wherein the configuration data, when loaded onto an instance of the one or more arrays of CGR units of the CGR processor, causes the one or more arrays of CGR units to implement at least the section of the dataflow graph; and
storing the configuration data in a non-transitory computer-readable storage medium.
2. The computer-implemented method of claim 1 , wherein the sectioning prefers section boundaries that combine section intermediate results with checkpoints.
3. The computer-implemented method of claim 1 , further comprising:
inserting a re-computation of a second data element based at least in part on the performance information for a second section of the plurality of sections indicating inadequate memory resources for at least the second section of the plurality of sections.
4. A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising:
sectioning a dataflow graph of a high-level program into a plurality of sections, the high-level program to be transformed into configuration data executable by a coarse-grained reconfigurable (CGR) processor including one or more arrays of CGR units, wherein the plurality of sections are to be mapped to the one or more arrays of CGR units of the CGR processor;
extracting performance information for each of the plurality of sections;
assigning a section of the plurality of sections that includes at least two computations dependent on a first data element to one or more CGR units of the CGR processor, wherein the first data element is loaded from a memory;
scheduling an additional load of the first data element to from the memory based at least in part on the performance information for the section indicating available memory bandwidth for that section;
eliminating, from the section, a buffer between a load of the first data element from the memory and one of the two computations dependent on the first data element;
and
generating the configuration data for the CGR processor including placed positions, data routing, and communication channels, wherein the configuration data, when loaded onto an instance of the one or more arrays of CGR units of the CGR processor, causes the one or more arrays of CGR units to implement at least the section of the dataflow graph.
5. The non-transitory computer-readable storage medium of claim 4 , wherein the sectioning prefers section boundaries that combine section intermediate results with checkpoints.
6. The non-transitory computer-readable storage medium of claim 4 , the method further comprising:
inserting a re-computation of a second data element based at least in part on the performance information for a second section of the plurality of sections indicating inadequate memory resources for at least the second section of the plurality of sections.
7. A system including one or more processors coupled to a memory, the memory loaded with computer program instructions, wherein the computer program instructions, when executed on the one or more processors, implement actions comprising:
sectioning a dataflow graph of a high-level program into a plurality of sections, the high-level program to be transformed into configuration data executable by a coarse-grained reconfigurable (CGR) processor including one or more arrays of CGR units, wherein the plurality of sections are to be mapped to the one or more arrays of CGR units of the CGR processor,
extracting performance information for each of the plurality of sections;
assigning a section of the plurality of sections that includes at least two computations dependent on a first data element to one or more CGR units of the CGR processor, wherein the first data element is loaded from a memory;
scheduling an additional load of the first data element from the memory based at least in part on the performance information for the section indicating available memory bandwidth for that section;
eliminating, from the section, a buffer between a load of the first data element from the memory and one of the two computations dependent on the first data element; and
generating the configuration data for the CGR processor including placed positions, data routing and communication channels, wherein the configuration data, when loaded onto an instance of the one or more arrays of CGR units of the CGR processor, causes the one or more arrays of CGR units to implement the at least section of the dataflow graph.
8. The computer-implemented method of claim 7 , wherein the sectioning prefers section boundaries that combine section intermediate results with checkpoints.
9. The computer-implemented method of claim 7 , further comprising:
inserting a re-computation of a second data element based at least in part on the performance information for a second section of the plurality of sections indicating inadequate memory resources for at least the second section of the plurality of sections.