Lossless tiling in convolution networks—tiling configuration for a sequence of sections of a graph
Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.
1. A data processing system, comprising:
compile time logic configured to
section a graph into a sequence of sections, the sequence of sections including at least a first section and a second section,
configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and
configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section,
wherein the first topology of tiling configurations is different from the second topology of tiling configurations; and
runtime logic configured with the compile time logic to
execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and
execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations, and
wherein the graph is a convolutional neural network, sections in the sequence of sections are forward pass subgraphs, wherein the sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are image data, wherein the inputs, intermediate outputs, and final outputs of the second section are image data.
2. The data processing system of claim 1 , wherein the first topology of tiling configurations is determined based on a number of processing nodes in the first section.
3. The data processing system of claim 1 , wherein the first topology of tiling configurations is determined based on respective processing logics implemented by respective processing nodes in the first section.
4. The data processing system of claim 1 , wherein the first topology of tiling configurations is determined based on a size of the inputs of the first section.
5. The data processing system of claim 1 , wherein the first topology of tiling configurations is determined based on a size of the final outputs of the first section.
6. The data processing system of claim 1 , wherein the second topology of tiling configurations is determined based on one or more of (i) a number of processing nodes in the second section, (ii) respective processing logics implemented by respective processing nodes in the second section, (iii) on a size of the inputs of the second section, and (iv) a size of the final outputs of the second section.
7. The data processing system of claim 1 , wherein the sequence of sections includes at least a third section, wherein the compile time logic is further configured to configure the third section with a third topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the third section, wherein the third topology of tiling configurations is different from the first topology of tiling configurations and the second topology of tiling configurations; and wherein the runtime logic is further configured to execute the third section to generate the inputs, intermediate outputs, and final outputs of the third section in the third topology of tiling configurations.
8. The data processing system of claim 1 , wherein the first topology of tiling configurations includes respective tiling configurations for the inputs, intermediate outputs, and final outputs of the first section.
9. The data processing system of claim 1 , wherein the graph is a convolutional neural network, wherein sections in the sequence of sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are input gradients, and wherein the inputs, intermediate outputs, and final outputs of the second section are input gradients.
10. The data processing system of claim 1 , wherein the final outputs of the first section have a non-overlapping final tiling configuration, the intermediate outputs of the first section have corresponding one or more overlapping intermediate tiling configurations, and the input of the first section has an overlapping input tiling configuration.
11. The data processing system of claim 1 , wherein the compile time logic is further configured to:
determine, for the first section, the first topology of tiling configurations by starting from the final outputs of the first section, and reverse traversing through the intermediate outputs of the first section, and ending with the inputs of the first section.
12. A computer implemented method for executing sections of a graph, the method comprising:
sectioning a data flow graph into a sequence of sections, the sequence of sections including at least a first section and a second section;
configuring the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section;
configuring the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section, wherein the first topology of tiling configurations is different from the second topology of tiling configurations;
executing the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations; and
executing the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations, and
wherein the graph is a convolutional neural network, sections in the sequence of sections are forward pass subgraphs, wherein the sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are image data, wherein the inputs, intermediate outputs, and final outputs of the second section are image data.
13. The method of claim 12 , further comprising:
determining the first topology of tiling configurations, based on one or more of (i) a number of processing nodes in the first section, (ii) respective processing logics implemented by respective processing nodes in the first section, (iii) a size of the inputs of the first section, and (iv) a size of the final outputs of the first section.
14. The method of claim 12 , further comprising:
determining the second topology of tiling configurations, based on one or more of (i) a number of processing nodes in the second section, (ii) respective processing logics implemented by respective processing nodes in the second section, (iii) on a size of the inputs of the second section, and (iv) a size of the final outputs of the second section.
15. The method of claim 12 , wherein the first topology of tiling configurations includes respective tiling configurations for the inputs, intermediate outputs, and final outputs of the first section.
16. The method of claim 12 , wherein the graph is a convolutional neural network, sections in the sequence of sections are forward pass subgraphs, wherein the sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are image data, wherein the inputs, intermediate outputs, and final outputs of the second section are image data.
17. The method of claim 12 , wherein the graph is a convolutional neural network, wherein
sections in the sequence of sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are input gradients, and wherein the inputs, intermediate outputs, and final outputs of the second section are input gradients.
18. A non-transitory computer readable storage medium impressed with computer program
instructions, the instructions, when executed on a processor, implement a method comprising:
sectioning a data flow graph into a sequence of sections, the sequence of sections including at least a first section and a second section;
configuring the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section;
configuring the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section, wherein the first topology of tiling configurations is different from the second topology of tiling configurations;
executing the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations; and
executing the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations, and
wherein the graph is a convolutional neural network, sections in the sequence of sections are forward pass subgraphs, wherein the sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are image data, wherein the inputs, intermediate outputs, and final outputs of the second section are image data.
19. The non-transitory computer readable storage medium of claim 18 , wherein the final outputs of the first section have a non-overlapping final tiling configuration, the intermediate outputs of the first section have corresponding one or more overlapping intermediate tiling configurations, and the input of the first section has an overlapping input tiling configuration.