Switches With A Watchdog Timer For Use In An Internal Network Of A Processor
A processor includes an internal network with separate packet-switching networks for request, response, data, and credit transmission. Each of the four networks includes switches interconnected by links. Interface circuits connect the internal network to communication links or electronic memory and communicate over the internal network. A network recovery circuit is also coupled to the internal network. Each switch has ports, buffers for input packets, routing circuitry to send packets to output ports based on destinations, and a watchdog timer to detect packet timeouts and notify the network recovery circuit of delays. The network recovery circuit responds to timeout messages by setting a network failure condition, ensuring efficient and reliable network operation.
1 . A method for detecting a network failure in an internal network that is internal to an integrated circuit or multi-chip module and includes a request network used to request transactions on the internal network, a response network used to send responses to the transactions requested on the request network, a data network used to transmit data for the transactions requested on the request network, and a credit network used to transmit credit tokens that manage traffic on the internal network, the request network, the response network, the data network, and the credit network configured to operate concurrently as separate packet-switching networks and having a plurality of links connected by a plurality of switches, the method comprising:
sending, a request packet over the request network from a first interface circuit to a second interface circuit, the request packet moving through one or more request switches of the plurality of switches;
receive a response packet over the response network from the second interface circuit at the first interface circuit, the response packet moving through one or more response switches of the plurality of switches;
transferring a data packet through the data network between the first interface circuit and the second interface circuit, the data packet moving through one or more data switches of the plurality of switches;
transferring a credit packet through the credit network between the first interface circuit and the second interface circuit, the credit packet moving through one or more credit switches of the plurality of switches;
exchanging hop credits between adjacent switches of the plurality of switches to manage a flow of packets through the adjacent switches;
receiving a packet at an input of a switch of the plurality of switches, wherein the packet is the request packet, the response packet, the data packet, or the credit packet;
storing the packet in a buffer in the switch;
determining an output port of the switch for the packet based on a header of the packet;
holding the packet in the buffer until enough hop credits are accumulated for the output port to accommodate the packet before sending the packet through the output port, wherein a number of credits accumulated for the output port are based on previously received hop credits;
monitoring an amount of time that the packet is held in the buffer before it is sent on the output port;
in response to the packet being held in the buffer for longer than a timeout period, sending a timeout message to a network recovery circuit; and
setting a network failure condition in the network recovery circuit in response to receiving the timeout message.
2 . The method of claim 1 , further comprising sending the timeout message from the switch to the network recovery circuit over the response network.
3 . The method of claim 1 , further comprising sending an interrupt to a host computer through an external communication link in response to the network failure condition being set.
4 . The method of claim 1 , further comprising stopping execution of an application using the internal network in response to the network failure condition being set.
5 . A processor comprising:
an internal network having a request network used to request transactions on the internal network, a response network used to send responses to the transactions requested on the request network, a data network used to transmit data for the transactions requested on the request network, and a credit network used to transmit credit tokens that manage traffic on the internal network, the request network, the response network, the data network, and the credit network configured to operate concurrently as separate packet-switching networks and having a plurality of links connected by a plurality of switches;
a plurality of interface circuits coupled between the internal network and either a communication link or an electronic memory, the plurality of interface circuits configured to communicate with each other over the internal network; and
a network recovery circuit coupled to the internal network;
a switch of the plurality of switches comprising:
a plurality of ports;
a plurality of buffers associated with respective ports of the plurality of ports to store input packets received through input ports of the plurality of ports;
routing circuitry coupled to the plurality of buffers and configured to send the input packets stored in the plurality of buffers to respective output ports of the plurality of ports based on their respective destinations; and
a watchdog timer configured to determine that a packet of the input packets has been stored in the plurality of buffers for longer than a timeout period without being sent, and send a timeout message to the network recovery circuit in response; and
the network recovery circuit configured to receive the timeout message and set a network failure condition in response.
6 . The processor of claim 5 , wherein the timeout message is sent over the response network.
7 . The processor of claim 5 , further comprising a force-quit controller configurable to stop execution of an application on at least a portion of the processor in response to the network failure condition being set.
8 . The processor of claim 5 , the plurality of interface circuits including a host interface circuit, coupled to an external communication link, configurable to send an interrupt to a host computer through the external communication link in response to the network failure condition being set.
9 . The processor of claim 8 , wherein the external communication link comprises a PCIe (Peripheral Component Interconnect Express) link or an Ethernet link.
10 . The processor of claim 8 , wherein host interface circuit includes the network recovery circuit.
11 . The processor of claim 5 , the plurality of interface circuits including an interface configurable unit, and a memory interface circuit, the processor further comprising:
an array of configurable units including the interface configurable unit, a plurality of processing units, and a plurality of memory units coupled together by an array level network, wherein the interface configurable unit is configurable to enable communication of application data between a configurable unit in array of configurable units and an external electronic memory coupled to the memory interface circuit over the internal network.
12 . A computing system comprising:
a plurality of external communication links including a first external communication link and a second external communication link;
an external device coupled to the first external communication link;
a host computer coupled to the second external communication link; and
a CGRP (coarse-grained reconfigurable processor), coupled to both the first external communication link and the second external communication link, the CGRP comprising an internal network and a network recovery circuit coupled to the internal network, the internal network having a request network used to request transactions on the internal network, a response network used to send responses to the transactions requested on the request network, a data network used to transmit data for the transactions requested on the request network, and a credit network used to transmit credit tokens that manage traffic on the internal network, the request network, the response network, the data network, and the credit network configured to operate concurrently as separate packet-switching networks and having a plurality of links connected by a plurality of switches;
a switch of the plurality of switches comprising:
a plurality of ports;
a plurality of buffers associated with respective ports of the plurality of ports to store input packets receive through the plurality of ports;
routing circuitry coupled to the plurality of buffers configured to send the input packets stored in the plurality of buffers to respective ports of the plurality of ports based on their respective destinations; and
a watchdog timer configured to determine that a packet of the input packets has been stored in the plurality of buffers for longer than a timeout period without being sent, and send a timeout message to the network recovery circuit in response; and
the network recovery circuit configured to receive the timeout message and set a network failure condition in response.
13 . The computing system of claim 12 , wherein the timeout message is sent over the response network.
14 . The computing system of claim 12 , the CGRP further comprising a force-quit controller configurable to stop execution of an application on at least a portion of the CGRP in response to the network failure condition being set.
15 . The computing system of claim 12 , further comprising a plurality of interface circuits coupled to the internal network, the plurality of interface circuits configured to communicate with each other over the internal network;
the plurality of interface circuits including a host interface circuit, coupled to the second external communication link, configurable to send an interrupt to the host computer through the second external communication link in response to the network failure condition being set.
16 . The computing system of claim 15 , wherein the second external communication link comprises a PCIe (Peripheral Component Interconnect Express) link or an Ethernet link.
17 . The computing system of claim 15 , wherein the host interface circuit includes the network recovery circuit.
18 . The computing system of claim 15 , the plurality of interface circuits including an interface configurable unit, and a memory interface circuit, the CGRP further comprising:
an array of configurable units including the interface configurable unit, a plurality of processing units, and a plurality of memory units coupled together by an array level network, wherein the interface configurable unit is configurable to enable communication of application data between a configurable unit in array of configurable units and an external electronic memory coupled to the memory interface circuit over the internal network.