Hang Detection In A Coarse Grained Reconfigurable Architecture Processor

1 . A reconfigurable processor, comprising:

an array of configurable units configurable to execute an application instrumented with at least one progress milestone;

a control bus coupled to configurable units in the array of configurable units; and

a hang detection circuit coupled to the control bus and including a timer that resets in response to receiving a control signal via the control bus;

wherein a configurable unit in the array of configurable units sends the control signal, in response to completion of a progress milestone in the at least one progress milestone, to the hang detection circuit via the control bus; and

the hang detection circuit detects a hang condition in the execution of the application based on an expiration of the timer.

2 . The reconfigurable processor of claim 1 , the hang detection circuit further comprising:

a second timer that resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone;

wherein the hang detection circuit also detects the hang condition based on an expiration of either the timer or the second timer.

3 . The reconfigurable processor of claim 1 , the hang detection circuit further comprising:

a second timer that resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone;

wherein the hang detection circuit detects the hang condition based on an expiration of both the timer and the second timer.

4 . The reconfigurable processor of claim 1 , wherein the timer also resets in response to receiving a second control signal via the control bus that indicates completion of a second progress milestone in the at least one progress milestone.

5 . The reconfigurable processor of claim 1 , the array of configurable units coupled to an interface unit that includes the hang detection circuit.

6 . The reconfigurable processor of claim 1 , the hang detection circuit further comprising a force-quit controller that stops execution of the application on the array of configurable units in response to detecting the hang condition.

7 . The reconfigurable processor of claim 1 , further comprising:

an external interface circuit coupled to a host computer through an external communication link;

an internal network coupled to the external interface circuit; and

an internal interface circuit coupled to the internal network and the control bus, the internal interface circuit including the hang detection circuit;

wherein the hang detection circuit further sends a hang message to the external interface circuit over the internal network in response to detecting the hang condition.

8 . The reconfigurable processor of claim 7 , the external interface circuit further including a network recovery circuit that receives the hang message and sends an interrupt to the host computer through the external communication link in response.

9 . The reconfigurable processor of claim 7 , the internal interface circuit further including a force-quit controller, wherein the external interface circuit sends a force quit message to the force-quit controller over the internal network in response to receiving the hang message, wherein the force-quit controller stops execution of the application on the array of configurable units in response to receiving the hang message.

10 . The reconfigurable processor of claim 7 , wherein internal network comprises a non-blocking dimensionally-routed mesh network.

11 . A method for detecting an application that has hung during execution in an array of configurable units having a control bus, the method comprising:

setting a timer in a hang detection circuit to a timeout value, the hang detection circuit coupled to the control bus;

in response to encountering a progress milestone during execution of the application in the array of configurable units, sending a control signal via a control bus from a configurable unit in the array of configurable units to the hang detection circuit;

resetting the timer in response to receiving the control signal via the control bus; and

in response to the timer expiring, detecting a hang condition.

12 . The method of claim 11 , further comprising stopping execution of the application on the array of configurable units in response to detecting the hang condition.

13 . The method of claim 11 , further comprising:

receiving a dataflow graph application for compilation;

inserting the progress milestone into the dataflow graph application to generate an instrumented dataflow graph application;

compiling the instrumented dataflow graph application to generate a configuration file; and

loading the configuration file into the array of configurable units and initiate execution of the instrumented dataflow graph application as the application.

14 . The method of claim 11 , further comprising:

determining a value for the timer based on an expected time between times that the progress milestone is to be encountered during execution of the application; and

initiating the timer with the value.

15 . The method of claim 11 , further comprising:

sending a hang message to an external interface circuit over an internal network coupling the array of configurable units to the external interface circuit in response to detecting the hang condition; and

sending an interrupt from the external interface circuit to a host computer through an external communication link in response to receiving the hang message.

16 . The method of claim 15 , further comprising:

sending a force quit message to a force-quit controller over the internal network in response to receiving the hang message; and

stopping execution of the application on the array of configurable units in response to receiving the force quit message.

17 . A computing system comprising:

a host computer;

an external communication link;

a coarse-grained reconfigurable architecture processor that includes:

an external interface circuit coupled to the host computer through the external communication link;

an internal network coupled to the external interface circuit;

an array of configurable units configurable to execute an application instrumented with at least one progress milestone;

a control bus coupled to configurable units in the array of configurable units;

an internal interface circuit coupled to the internal network and the control bus, the internal interface circuit including hang detection circuit with a timer that resets in response to receiving a control signal via the control bus;

wherein a configurable unit in the array of configurable units sends the control signal, in response to completion of a progress milestone of the at least one progress milestone, to the hang detection circuit via the control bus; and

the hang detection circuit detects a hang condition in the execution of the application based on an expiration of the timer.

18 . The computing system of claim 17 , wherein the hang detection circuit sends a hang message to the external interface circuit over the internal network in response to detecting the hang condition.

19 . The computing system of claim 18 , wherein the external interface circuit sends an interrupt to the host computer through the external communication link in response to receiving the hang message.

20 . The computing system of claim 18 , the internal interface circuit further including a force-quit controller, wherein the external interface circuit sends a force quit message to the force-quit controller over the internal network in response to receiving the hang message, wherein the force-quit controller stops execution of the application on the array of configurable units in response to receiving the hang message.