IP Library Granted Patent US 12,254,300
Granted Patent B2
US 12,254,300 · App. 17/974,910 · Granted Mar 18, 2025

Merging buffer access operations in a coarse-grained reconfigurable computing system

Inventors: David Alan Koeplinger (Palo Alto, CA); Adam Bordelon (Palo Alto, CA); Weihang Fan (Mountain View, CA); Kevin Brown (Palo Alto, CA); Weiwei Chen (Palo Alto, CA)
Assignee: SambaNova Systems, Inc.
G06F8/45G06F8/433G06F8/4441G06F2212/1041
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Quick Facts
Patent No.
US 12,254,300
App. No.
17/974,910
Granted
Mar 18, 2025
Kind
B2
Abstract

A method for merging buffers and associated operations includes receiving a compute graph for a reconfigurable dataflow computing system and conducting a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation. The buffer allocation and merging process may include replacing the first operation node and the consuming node with a merged buffer node within the graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and that the resource cost of the merged node is less than the sum of the resource costs of separate buffer nodes. A corresponding system and computer readable medium are also disclosed herein.

Claims (34)

1. A system for merging buffers and associated operations in a reconfigurable computing environment, the system comprising:

an allocation module configured to receive a compute graph for a reconfigurable dataflow computing system, the compute graph comprising operation nodes that specify operations and edges that specify producer and consumer relationships between operations;

the allocation module configured to conduct a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation; and

wherein the buffer allocation and merging process comprises allocating a merged buffer node and replacing the first operation node and the exactly one consuming node with the merged buffer node within the compute graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and responsive to determining that a resource cost of the merged buffer node is less than a sum of resource costs for separate buffer nodes for the first operation and the second operation.

2. The system of claim 1 , wherein the separate buffer nodes comprise a first buffer node and a second buffer node.

3. The system of claim 2 , wherein the buffer allocation and merging process comprises allocating the first buffer node that specifies the memory indexing operation and the second buffer node that specifies the second operation.

4. The system of claim 3 , wherein the buffer allocation and merging process comprises merging the first buffer node and the second buffer node into the merged buffer node.

5. The system of claim 1 , wherein the merged buffer node specifies the merged indexing operation.

6. The system of claim 1 , wherein determining that the first operation and the second operation can be merged into the merged indexing operation comprises accessing an operation merging compatibility table.

7. The system of claim 1 , wherein the first operation is a read-side operation or a write-side operation.

8. The system of claim 1 , wherein the second operation is a read-side operation or a write-side operation.

9. The system of claim 1 , wherein the first operation is selected from the group consisting of a layout cast operation, a permute view operation, a reshape operation, a split view operation, a vector transpose operation, a logical transpose operation, a physical transpose operation and a temporal operation.

10. The system of claim 1 , wherein the second operation is selected from the group consisting of a layout cast operation, a permute view operation, a reshape operation, a split view operation, a vector transpose operation, a logical transpose operation, a physical transpose operation and a temporal operation.

11. The system of claim 1 , further comprising a configuration module configured to generate configuration information that enables the reconfigurable dataflow computing system to execute a dataflow computing task corresponding to the compute graph including the merged buffer node.

12. The system of claim 11 , further comprising a runtime module configured to configure the reconfigurable dataflow computing system using the configuration information.

13. The system of claim 12 , the runtime module further configured to launch execution of the dataflow computing task on a coarse-grained reconfigurable (CGR) processor.

14. A method for merging buffers and associated operations in a reconfigurable computing system, the method comprising:

receiving a compute graph for a reconfigurable dataflow computing system, the compute graph comprising operation nodes that specify operations and edges that specify producer and consumer relationships between operations;

conducting a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation;

wherein the buffer allocation and merging process allocating a merged buffer node and replacing the first operation node and the exactly one consuming node with the merged buffer node within the compute graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and responsive to determining that a resource cost of the merged buffer node is less than a sum of resource costs for separate buffer nodes for the first operation and the second operation.

15. The method of claim 14 , wherein the separate buffer nodes comprise a first buffer node and a second buffer node.

16. The method of claim 15 , wherein the buffer allocation and merging process comprises allocating the first buffer node that specifies the memory indexing operation and the second buffer node that specifies the second operation.

17. The method of claim 16 , wherein the buffer allocation and merging process comprises merging the first buffer node and the second buffer node into the merged buffer node.

18. The method of claim 14 , wherein determining that the first operation and the second operation can be merged into a merged indexing operation comprises accessing an operation merging compatibility table.

19. The method of claim 14 , wherein the first operation is a read-side operation or a write-side operation.

20. The method of claim 14 , wherein the second operation is a read-side operation or a write-side operation.

21. The method of claim 14 , wherein the first operation is selected from the group consisting of a layout cast operation, a permute view operation, a reshape operation, a split view operation, a vector transpose operation, a logical transpose operation, a physical transpose operation and a temporal operation.

22. The method of claim 14 , wherein the second operation is selected from the group consisting of a layout cast operation, a permute view operation, a reshape operation, a split view operation, a vector transpose operation, a logical transpose operation, a physical transpose operation and a temporal operation.

23. The method of claim 15 , further comprising deleting the first buffer node and the second buffer node responsive to determining that the first operation and the second operation cannot be merged into a merged indexing operation.

24. The method of claim 15 , further comprising deleting the first buffer node and the second buffer node responsive to determining that the resource cost of the merged buffer node is greater than the sum of the resource costs of the first buffer node and the second buffer node.

25. A non-transitory computer-readable medium having instructions encoded thereon for conducting a method for merging buffers and associated operations in a reconfigurable computing system, the method comprising:

receiving a compute graph for a reconfigurable dataflow computing system, the compute graph comprising operation nodes that specify operations and edges that specify producer and consumer relationships between operations;

conducting a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation;

wherein the buffer allocation and merging process allocating a merged buffer node and replacing the first operation node and the exactly one consuming node with the merged buffer node within the compute graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and responsive to determining that a resource cost of the merged buffer node is less than a sum of resource costs for separate buffer nodes for the first operation and the second operation.

Assignments (2)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2023
From: KOEPLINGER, DAVID ALEN; BORDELON, ADAM; FAN, WEIHANG; BROWN, KEVIN; CHEN, WEIWEI
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 064558/0474 →
Continuity (2)
Provisional Application 63328128 · Apr 6, 2022
Related Publication 20230325312A1 · Oct 12, 2023
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