Routing circuits for defect repair for a reconfigurable data processor
A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.
1. A system comprising:
a plurality of homogeneous rows of processors spatially arranged as rows 0 to N+1;
configurable logic to route packets of data to processors of the plurality of homogeneous rows of processors;
a parameter store storing data indicating a tagged row X (where 0≤X≤N) of the plurality of homogeneous rows of processors; and
a configuration controller to load configuration row data that implements at least a portion of an executable graph using a subset of N or fewer rows of the plurality of homogeneous rows of processors, excluding the tagged row in dependence on the data in the parameter store, by configuring the configurable logic to load row Y configuration data of the configuration row data into row Y of the plurality of homogeneous rows of processors (where 0≤Y<X) and to load row Z configuration data of the configuration row data into row Z+1 of the plurality of homogeneous rows of processors (where X≤Z≤N).
2. The system of claim 1 , wherein the plurality of homogeneous rows of processors, the configurable logic, the parameter store, and the configuration controller are on a single integrated circuit die.
3. The system of claim 1 , wherein the configurable logic includes a plurality of rows of switches interleaved with the plurality of homogeneous rows of processors, a second switch in a second row of the plurality of rows of switches including:
a first input port connected to an output port of a first switch in a first row of the plurality of rows of switches, the first row of the plurality of rows of switches adjacent to the second row of the plurality of rows of switches;
a first output port connected to an input port of a third switch in a third row of the plurality of rows of switches, the third row of the plurality of rows of switches adjacent to the second row of the plurality of rows of switches on an opposite side from the first row of the plurality of rows of switches;
a second output port connected to a first processor in row M (where 0≤M≤N) of the plurality of homogeneous rows of processors;
routing logic to forward a data packet having a destination of the first processor received on the first input port of the second switch to either the first output port of the second switch or the second output port of the second switch, dependent upon the data in the parameter store.
4. The system of claim 3 , wherein M<X and the routing logic to forward the data packet to the first processor through the second output port of the second switch.
5. The system of claim 3 , wherein X≤M and the routing logic to forward the data packet to the third switch through the first output port of the second switch.
6. The system of claim 3 , the second switch in the second row of the plurality of rows of switches also including a third output port connected to an input port of a fourth switch in the second row of the plurality of rows of switches;
the routing logic to further forward a data packet having a destination of a second processor in row M of the plurality of homogeneous rows of processors received on the first input port of the second switch to either the first output port of the second switch or the third output port of the second switch, dependent upon the data in the parameter store.
7. The system of claim 6 , wherein M<X and the routing logic to forward the data packet to the fourth switch through the third output port of the second switch.
8. The system of claim 6 , wherein X≤M and the routing logic to forward the data packet to the third switch through the first output port of the second switch.
9. The system of claim 1 , wherein the configurable logic routes packets having a destination of a first processor in the tagged row to a second processor that is not in the tagged row, based on the data in the parameter store.
10. The system of claim 9 , wherein the packets carry a route identifier, and the routing logic includes a table mapping the route identifiers to output ports on the second switch, and wherein the table is configured in dependence on the data in the parameter store.
11. The system of claim 1 , including:
a control signal path arranged in a daisy chain from the configuration controller through at least some of the processors in the plurality of homogeneous rows of processors; and
logic circuits to configure the control signal path to bypass the processors in the tagged row of the plurality of homogeneous rows of processors in dependence on the data in the parameter store.
12. The system of claim 1 , wherein the configurable logic defines routes responsive to the data in the parameter store to route packets having a destination of a first processor in the tagged row of the plurality of homogeneous rows of processors to a second processor that is not in the tagged row of the plurality of homogeneous rows of processors.
13. The system of claim 1 , wherein the configurable logic includes a plurality of rows of switches interleaved with the plurality of homogeneous rows of processors, and the configuration controller assigns virtual addresses to processors in the plurality of homogeneous rows of processors in dependence on the data in the parameter store, switches of the plurality of rows of switches including:
input ports and output ports connecting to other switches in the plurality of rows of switches;
input ports and output ports connecting to processors in the plurality of homogeneous rows of processors; and
routing logic, responsive to the virtual addresses, to forward data packets having a destination processor received on an input port a switch of the plurality of rows of switches to an output port of the switch.
14. A method for avoiding use of a tagged row of processors in a plurality of homogeneous rows of processors spatially arranged as rows 0 to N+ 1 , the method comprising:
retrieving data from a parameter store, the data indicating a tagged row X (where 0 ≤X ≤N) of the plurality of homogeneous rows of processors;
obtaining configuration data that implements at least a portion of an executable graph using K+ 1 rows (where K≤N) of the plurality of homogeneous rows of processors;
loading, through configurable logic coupled to processors of the plurality of homogenous rows of processors, a first subset of the configuration data for rows 0 through X- 1 into processors of rows 0 through X- 1 of the plurality of homogenous rows of processors; and
loading, through the configurable logic, a second subset of the configuration data for rows X through K into processors of rows X+ 1 through K+ 1 of the plurality of homogenous rows of processors.
15. The method of claim 14 , wherein the configurable logic includes a plurality of rows of switches interleaved with the plurality of homogeneous rows of processors, including a first switch connected to a first processor in row M of the plurality of homogenous rows of processors, the method further comprising:
receiving, at a first input port of the first switch, a data packet having a destination of the first processor;
responsive to determining that M<X, sending the data packet through a first output port to the first processor; and
responsive to determining that X<M, sending the data packet through a second output port to a second switch connected to a processor in row M+ 1 of the plurality of homogeneous rows of processors.
16. The method of claim 14 , wherein the configurable logic includes a plurality of rows of switches interleaved with the plurality of homogeneous rows of processors, including a first switch connected to a first processor in row M of the plurality of homogenous rows of processors, the method further comprising:
receiving, at a first input port of the first switch, a data packet having a destination of a second processor in row M of the plurality of homogenous rows of processors;
responsive to determining that X≤M, sending the data packet through a second output port to a second switch of the plurality of homogeneous rows of switches connected to a processor in row M+ 1 of the plurality of homogeneous rows of processors; and
responsive to determining that M<X, sending the data packet through a third output port to a third switch of the plurality of homogeneous rows of switches connected to a processor in row M of the plurality of homogeneous rows of processors.
17. The method of claim 14 , further comprising:
obtaining, during execution of the executable graph, a first data packet having a destination of a first processor in row L (where L<X) of the plurality of homogenous rows of processors;
sending, through the configurable logic, the first data packet to the first processor in row L of the plurality of homogenous rows of processors;
obtaining, during execution of the executable graph, a second data packet having a destination of a first processor in row M (where X≤M) of the plurality of homogenous rows of processors;
sending, through the configurable logic, the second data packet to a first processor in row M+1 of the plurality of homogenous rows of processors.
18. The method of claim 14 , including defining routes through the configurable logic responsive to the data retrieved from the parameter store to route a data packet having a destination of a first processor in the tagged row of the plurality of homogeneous rows of processors to a second processor that is not in the tagged row of the plurality of homogeneous rows of processors.
19. The method of claim 18 , wherein the data packet includes a route identifier, the method further including mapping the route identifier to an output port on a switch in the configurable logic using a mapping table configured in dependence on the data retrieved from the parameter store.
20. The method of claim 14 , wherein the configurable logic includes a plurality of rows of switches interleaved with the plurality of homogeneous rows of processors, the method further including assigning virtual addresses to processors in the plurality of homogeneous rows of processors in dependence on the data retrieved from the parameter store, and routing, responsive to the virtual addresses, data packets received on an input port on a switch of the plurality of rows of switches to an output port on the switch.
21. The method of claim 14 , wherein the configurable logic includes an array of switches having flow tables, the method further including modifying the flow tables in dependence on the data retrieved from the parameter store.