Method for scanning a memory array
A method is disclosed for scanning an array of memory cells arranged in rows and columns, where the array includes a scan chain partitioned into multiple sections. Each section includes a first scan multiplexer, a section buffer cell, and multiple memory cells. The method includes determining whether a scan shift mode is entered, asserting a scan enable signal to select second inputs of each first scan multiplexer when the scan shift mode is entered, coupling the scan input with the input of the section buffer cell of the first section, and coupling the output of the memory cell in the previous section with the input of the section buffer cell in the next section. The method further includes updating the contents of the section buffer cell and the memory cells using clock signals and scan word line pulses.
1 . A method of scanning an array of memory cells arranged in R rows numbered 0 through R−1, and C columns numbered 0 through C−1, the array comprising a scan chain partitioned into at least two sections of each at least a part of a column comprising two or more cells, the at least two sections coupled in series between a scan input SI and a scan output SO, and each section comprising a first scan multiplexer, a section buffer cell, and M memory cells numbered 0 through M−1, the method comprising:
(a) determining whether a scan shift mode is entered;
(b) upon determining that the scan shift mode is not entered, returning to (a);
(c) upon determining that the scan shift mode is entered, asserting a scan enable signal SE to select second inputs of each first scan multiplexer;
(d) coupling the scan input SI with an input of the section buffer cell of a first of the at least two sections, and for each section s, wherein s ranges from 0 to S−2, coupling an output of memory cell in row M−1 with an input of the section buffer cell in section s+1;
(e) asserting and de-asserting a clock signal CLK to update contents of the section buffer cell of each of the at least two sections;
(f) for each of the at least two sections, and each memory cell m in a section, wherein m ranges backwards from M−1 to 1, coupling an input of memory cell m with an output of memory cell m−1, and asserting and de-asserting a single scan word line SWL pulse to update contents of the memory cell; and
(g) for each of the at least two sections, and each memory cell m=0 in a section, coupling an input of memory cell m with an output of the section buffer cell, and asserting and de-asserting a single scan word line SWL pulse to update contents of the memory cell.
2 . The method of claim 1 , wherein:
each section further comprises a second scan multiplexer and a read multiplexer; and
coupling an input of memory cell m with an output of memory cell m−1 includes routing an output signal of memory cell m−1 via the read multiplexer and the second scan multiplexer.
3 . The method of claim 1 , wherein:
memory cells contents in a section are updated with successive non-overlapping scan word line SWL pulses.