Peer-to-peer route through in a reconfigurable computing system
A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.
1. A reconfigurable dataflow unit (RDU) comprising:
an intra-RDU network;
a first interface circuit coupled between the intra-RDU network and a first external interconnect external to the RDU, wherein the RDU is a first RDU;
a second interface circuit coupled between the intra-RDU network and a second external interconnect external to the first RDU;
a third interface circuit coupled between the intra-RDU network and a third external interconnect external to the first RDU;
an array of configurable units having a coarse grain reconfigurable architecture and including a plurality of configurable processing units and a plurality of configurable memory units connected by an array level network;
one or more function interfaces that respectively provide a connection between the intra-RDU network and the array level network or another functional unit of the first RDU;
an identity register to store a first identifier for the first RDU; and
a pass-through table to store an interface circuit identifier for each of a plurality of other RDU identifiers, the interface circuit identifier capable of identifying one of at least the second interface circuit and the third interface circuit;
the first interface circuit comprising:
receiving circuitry to receive a first packet from the first external interconnect and extract a target RDU identifier from the first packet;
a comparator to compare the target RDU identifier to the first identifier;
target RDU circuitry to communicate over the intra-RDU network to a function interface of the one or more function interfaces based on information in the first packet in response to a determination by the comparator that the target RDU identifier is equal to the first identifier; and
pass-through RDU circuitry to access the pass-through table and retrieve the interface circuit identifier for the target RDU identifier and, in response to a determination by the comparator that the target RDU identifier is not equal to the first identifier, send the target RDU identifier and other information from the first packet to the second interface circuit over the intra-RDU network, wherein the interface circuit identifier for the target RDU identifier is equal to an identifier for the second interface circuit.
2. The RDU of claim 1 , wherein the RDU is implemented on a single integrated circuit die, or the RDU comprises two or more integrated circuit dies mounted in a multi-die package.
3. The RDU of claim 1 , the second interface circuit comprising forwarding circuitry to receive the target RDU identifier and the other information from the first packet over the intra-RDU network, create a second packet based on the target RDU identifier and other information from the first packet, and send the second packet over the second external interconnect.
4. The RDU of claim 3 , wherein the second external interconnect is coupled to a second RDU, the forwarding circuitry further comprising circuitry to determine an address for the second RDU and to use the address for the second RDU to send the second packet to the second RDU over the second external interconnect.
5. The RDU of claim 4 , wherein the circuitry to determine an address for the second RDU comprises a base address register table to provide addresses for a plurality of other RDUs, including the second RDU.
6. The RDU of claim 4 , wherein the circuitry to determine an address for the second RDU comprises a register to hold the address for the second RDU.
7. The RDU of claim 1 , wherein the function interface comprises a memory interface circuit coupled between the intra-RDU network and an external memory bus;
wherein the memory interface circuit is identified for communication over the intra-RDU network based on a memory address provided with the first packet.
8. The RDU of claim 1 , wherein the function interface comprises an array interface circuit coupled between the intra-RDU network and the array level network of the array of configurable units;
wherein the array interface circuit is identified for communication over the intra-RDU network based on an identifier of the array interface circuit provided in the first packet.
9. The RDU of claim 1 , the first interface circuit further comprising a hung array bit to indicate that communication with the array of configurable units over the intra-RDU network should be suppressed;
the target RDU circuitry further comprising circuitry to evaluate the hung array bit and in response to the hung array bit being set with the target RDU identifier equal to the first identifier and the function interface being an identifier for an array interface in the array of configurable units, sending a response to the first packet back on the first external interconnect without communicating over the intra-RDU network.
10. The RDU of claim 1 , the first packet also including a transaction type with the first interface circuit capable to recognize transaction types of:
a stream write to a first configurable memory unit in the array of configurable units;
a stream clear to send (SCTS) to a second configurable memory unit in the array of configurable units;
a remote write to a memory controller of the RDU;
a remote read request to the memory controller of the RDU;
a remote read completion to a third configurable memory unit in the array of configurable units;
a barrier request; and
a barrier completion to a fourth configurable memory unit in the array of configurable units.
11. A method for routing packets in a computing system that includes three or more reconfigurable dataflow units (RDUs) each having a coarse grain reconfigurable architecture, the method comprising:
receiving, over a first external interconnect at a first interface circuit of a first RDU of the three or more RDUs, a first packet;
extracting a target RDU identifier from the first packet;
determining whether the target RDU identifier identifies the first RDU;
in response to determining that the target RDU identifier identifies the first RDU, communicating over a switching array fabric of the first RDU to a function interface of the first RDU identified in the first packet to perform a transaction indicated by the first packet; and
in response to determining that the target RDU identifier does not identify the first RDU, accessing a pass-through table to retrieve an interface circuit identifier for the target RDU identifier that identifies a second interface of the first RDU coupled to a second external interconnect that is also coupled to a second RDU of the three or more RDUs, and sending the target RDU identifier and other information from the first packet to the second interface over the switching array fabric of the first RDU.
12. The method of claim 11 , further comprising:
identifying a memory interface circuit coupled between the switching array fabric and an external memory bus as the function interface based on an address provided with the first packet;
sending a transaction type extracted from the first packet and the address from the first interface circuit to the memory interface circuit as a part of the communicating over the switching array fabric; and
accessing external memory coupled to the external memory bus, by the memory interface circuit, based on the transaction type and the address.
13. The method of claim 11 , further comprising:
identifying an array interface circuit coupled between the switching array fabric and an array level network of an array of configurable units comprising a plurality of configurable memory units and a plurality of processing units coupled together by the array level network as the function interface based on an identifier in the first packet;
sending a transaction type extracted from the first packet to the array interface circuit as a part of the communicating over the switching array fabric; and
communicating, by the array interface circuit, with a configurable memory unit in the array of configurable units over the array level network based on the transaction type, wherein an identity of the configurable memory unit is pre-configured in the array interface circuit.
14. The method of claim 11 , further comprising:
receiving, at the second interface of the first RDU over the switching array fabric, the target RDU identifier and the other information from the first packet;
creating, in the second interface, a second packet based on the target RDU identifier and other information from the first packet; and
sending the second packet over the second external interconnect to the second RDU.
15. The method of claim 14 , further comprising:
obtaining an address for the second RDU; and
using the address for the second RDU to send the second packet to the second RDU over the second external interconnect.
16. A computing system comprising three or more reconfigurable dataflow units (RDUs), each RDU of the three or more RDUs comprising:
an intra-RDU network;
an array of configurable units having a coarse grain reconfigurable architecture and including a plurality of configurable processing units and a plurality of configurable memory units connected by an array level network and an array interface circuit that provides a connection between the array level network and the intra-RDU network;
memory interface circuit coupled between the intra-RDU network and an external memory bus;
a plurality of external interconnects, each external interconnect of the plurality of external interconnects coupled to a respective port interface circuit in the RDU that is also coupled to the intra-RDU network;
an identity register to store an identifier for the RDU; and
a pass-through table to store a target port interface circuit identifier for each of a plurality of RDU identifiers;
each port interface circuit of the respective port interface circuits of an RDU of the three or more RDUs respectively comprising:
receiving circuitry to receive a first packet from its respective external interconnect and extract a first target RDU identifier from the first packet;
a comparator to compare the first target RDU identifier to the identifier stored in the identity register;
target RDU circuitry to communicate over the intra-RDU network to the array interface circuit or the memory interface circuit based on information in the first packet in response to a determination by the comparator that the first target RDU identifier is equal to the identifier;
pass-through RDU circuitry to access the pass-through table and retrieve the target port interface circuit identifier for the first target RDU identifier and, in response to a determination by the comparator that the first target RDU identifier is not equal to the identifier, send the first target RDU identifier and other information from the first packet to a port interface circuit of the RDU identified by the target port interface circuit identifier over the intra-RDU network; and
forwarding circuitry to receive a second target RDU identifier and other information over the intra-RDU network, create a second packet carrying the second target RDU identifier and the other information, and send the second packet over the respective external interconnect.
17. The computing system of claim 16 , wherein each RDU of a set of RDUs out of the three or more RDUs is connected to each other RDU in the set of RDUs through a respective external interconnect of the plurality of external interconnects.
18. The computing system of claim 17 , wherein the set of RDUs is organized in a ring topology and each RDU in the set of RDUs is also connected to each adjacent RDU in the ring topology through a second respective external interconnect of the plurality of external interconnects so that there are two interface circuits coupling adjacent RDUs in the ring topology.
19. The computing system of claim 18 , wherein the pass-through table is configured create counter-rotating dataflow rings using the two interface circuits coupling adjacent RDUs in the ring topology.
20. The computing system of claim 16 , wherein a set of RDUs out of the three or more RDUs is organized in a ring topology with each RDU in the set of RDUs connected to each adjacent RDU in the ring topology through a respective external interconnect of the plurality of external interconnects.