Instrumentation networks for data flow graphs
A reconfigurable processor comprises an array of processing units and an instrumentation network. The array of processing units is configured to execute runtime events to execute an application. The instrumentation network is operatively coupled to the array of processing units. The instrumentation network comprises a control bus configured to form control signal routes in the instrumentation network. The instrumentation network further comprises a plurality of instrumentation counters having inputs and outputs connected to the control bus and to the processing units. Instrumentation counters in the plurality instrumentation units are configurable to consume control signals on the inputs and produce counts of the runtime events on the outputs.
1. A reconfigurable processor, comprising:
an array of processing units configured to execute runtime events to execute an application; and
an instrumentation network operatively coupled to the array of processing units, the instrumentation network comprising:
a control bus configured to form control signal routes in the instrumentation network; and
a plurality of instrumentation counters having inputs and outputs connected to the control bus and to processing units in the array of processing units, instrumentation counters in the plurality instrumentation counters configurable to consume control signals on the inputs and produce counts of the runtime events on the outputs,
wherein the control signals are read ready tokens.
2. The reconfigurable processor of claim 1 , wherein the instrumentation network and the instrumentation counters are arranged inside the array of processing units.
3. The reconfigurable processor of claim 1 , wherein the instrumentation network and the instrumentation counters are arranged outside the array of processing units.
4. The reconfigurable processor of claim 1 , wherein the control signals are generated by the processing units.
5. The reconfigurable processor of claim 1 , wherein the control signals are read begun tokens.
6. The reconfigurable processor of claim 1 , wherein the control signals are read done tokens.
7. The reconfigurable processor of claim 1 , wherein the control signals are write ready tokens.
8. The reconfigurable processor of claim 1 , wherein the control signals are write begun tokens.
9. The reconfigurable processor of claim 1 , wherein the control signals are write done tokens.
10. The reconfigurable processor of claim 1 , wherein the control signals are barrier tokens.