Merging skip-buffers in a reconfigurable dataflow processor
A method in a reconfigurable computing system includes connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers, which generates a plurality of skip-buffers. The method includes determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge. The method also includes merging, wholly or partially, the compatible skip-buffers to produce a merged skip-buffer having a minimal buffer depth. The described method may reduce memory unit consumption and latency.
1. A system in a reconfigurable dataflow processor, the system comprising:
a host computer comprising a processor and an optimization module configured to conduct a method comprising:
connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers to produce a plurality of skip-buffers;
determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge to produce mergeable skip-buffers; and
merging, wholly or partially, the mergeable skip-buffers to produce a merged skip-buffer having a minimal buffer depth.
2. The system of claim 1 , wherein merging reduces memory unit consumption.
3. The system of claim 1 , wherein connecting, determining, and merging occur in a first intermediate stage of a coarse-grained reconfigurable compiler.
4. The system of claim 3 , wherein additional skip-buffer merging is conducted subsequent to the first intermediate stage of the coarse-grained reconfigurable compiler.
5. The system of claim 4 , wherein resource aware peephole optimization is conducted subsequent to the first intermediate stage of the coarse-grained reconfigurable compiler.
6. The system of claim 1 , wherein the mergeable skip-buffers have a minimal buffer depth.
7. The system of claim 1 , wherein determining that the skip-buffers of the plurality of skip-buffers are mergeable comprises determining that a first set of operations corresponding to the first set of tensor consumers are compatible with a second set of operations corresponding to the second set of tensor consumers.
8. The system of claim 1 , wherein the mergeable skip-buffers are partially mergeable and at least one mergeable skip-buffer of the mergeable skip-buffers has a buffer depth that is greater than the minimal buffer depth.
9. The system of claim 8 , wherein merging the mergeable skip-buffers produces an augmented buffer in addition to the merged skip-buffer.
10. A method in a reconfigurable computing system, the method comprising:
connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers to produce a plurality of skip-buffers;
determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge to produce mergeable skip-buffers; and
merging, wholly or partially, the mergeable skip-buffers to produce a merged skip-buffer having a minimal buffer depth.
11. The method of claim 10 , wherein merging reduces memory unit consumption.
12. The method of claim 10 , wherein connecting, determining, and merging occur in a first intermediate stage of a coarse-grained reconfigurable compiler.
13. The method of claim 12 , wherein additional skip-buffer merging is conducted subsequent to the first intermediate stage of the coarse-grained reconfigurable compiler.
14. The method of claim 13 , wherein resource aware peephole optimization is conducted subsequent to the first intermediate stage of the coarse-grained reconfigurable compiler.
15. The method of claim 10 , wherein the mergeable skip-buffers have a minimal buffer depth.
16. The method of claim 10 , wherein determining that the skip-buffers of the plurality of skip-buffers are mergeable comprises determining that a first set of operations corresponding to the first set of tensor consumers are compatible with a second set of operations corresponding to the second set of tensor consumers.
17. The method of claim 10 , wherein the mergeable skip-buffers are partially mergeable and at least one mergeable skip-buffer of the mergeable skip-buffers has a buffer depth that is greater than the minimal buffer depth.
18. The method of claim 17 , wherein merging the mergeable skip-buffers produces an augmented buffer in addition to the merged skip-buffer.
19. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, and wherein the program instructions are executable by a processor to cause the processor to conduct a method comprising:
connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers to produce a plurality of skip-buffers;
determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge to produce mergeable skip-buffers; and
merging, wholly or partially, the mergeable skip-buffers to produce a merged skip-buffer having a minimal buffer depth.