Fractional force-quit for reconfigurable processors
A reconfigurable data processor includes an array of configurable units. The array includes a two or more sub-arrays of configurable units, and sub-arrays of configurable units in the plurality of sub-arrays of configurable units are configurable to separately execute different programs. The reconfigurable data processor also includes a force-quit controller connected to the array. The force-quit controller can stop execution of a particular program on a particular sub-array of configurable units and reset the particular sub-array of configurable units, while remaining sub-arrays of configurable units continue execution of their respective programs.
1. A reconfigurable data processor, comprising:
an array of configurable units, the array including a plurality of sub-arrays of configurable units, and sub-arrays of configurable units in the plurality of sub-arrays of configurable units configurable to separately execute different programs; and
a force-quit controller connected to the array, configurable to stop execution of a particular program on a particular sub-array of configurable units in the plurality of sub-arrays of configurable units and reset the particular sub-array of configurable units, while remaining sub-arrays of configurable units in the plurality of sub-arrays of configurable units continue execution of remaining programs.
2. The reconfigurable data processor of claim 1 , wherein the force-quit controller is further configurable to respond to a force-quit command to stop the execution of the particular program on the particular sub-array of configurable units and reset the particular sub-array of configurable units.
3. The reconfigurable data processor of claim 2 , wherein the force-quit command is generated in response to an external event outside the array.
4. The reconfigurable data processor of claim 3 , wherein the force-quit command is generated by a runtime program running on a host processor connected to the array.
5. The reconfigurable data processor of claim 2 , wherein the force-quit command is generated in response to an internal event inside the array.
6. The reconfigurable data processor of claim 5 , wherein the force-quit command is generated by a program executing in the array.
7. The reconfigurable data processor of claim 2 , wherein the force-quit command is generated in response to the particular sub-array of configurable units becoming unresponsive.
8. The reconfigurable data processor of claim 7 , wherein the particular sub-array of configurable units becomes unresponsive due to a hardware bug.
9. The reconfigurable data processor of claim 7 , wherein the particular sub-array of configurable units becomes unresponsive due to a software bug.
10. The reconfigurable data processor of claim 1 , wherein the force-quit controller is further configurable to make the particular sub-array of configurable units available to execute a new program.
11. The reconfigurable data processor of claim 10 , wherein the force-quit controller is further configurable to make the particular sub-array of configurable units available to receive new commands from a runtime program.
12. The reconfigurable data processor of claim 1 , wherein each sub-array of configurable units in the plurality of sub-arrays of configurable units has a plurality of address generation and coalescing units (AGCUs), including a master AGCU.
13. The reconfigurable data processor of claim 12 , wherein a particular master AGCU of the particular sub-array of configurable units includes the force-quit controller.
14. The reconfigurable data processor of claim 13 , wherein respective sub-arrays in the plurality of sub-arrays of configurable units have respective master AGCUs that include respective force-quit controllers.
15. The reconfigurable data processor of claim 1 , wherein the force-quit controller is further configurable to cause configurable units in a particular sub-array of configurable units to clear their internal states.
16. The reconfigurable data processor of claim 1 , wherein the force-quit controller is further configurable to cause the configurable units to restore their credit counters.
17. The reconfigurable data processor of claim 1 , wherein the force-quit controller is further configurable to cause the configurable units to empty their input buffers and output buffers.
18. The reconfigurable data processor of claim 13 , wherein the force-quit controller is further configurable to cause the particular master AGCU to complete outstanding transactions on communication resources (top level network (TLN)) configurable to set up links between a configurable interconnect (array level network (ALN)) of the array and external data processing resources outside the array.
19. The reconfigurable data processor of claim 13 , wherein the force-quit controller is further configurable to cause the particular master AGCU to empty its input buffers and output buffers.
20. A computer-implemented method comprising:
loading and executing a first program on a first sub-array of configurable units of a plurality of sub-arrays of configurable units on a reconfigurable data processor;
loading and executing a second program on a second sub-array of configurable units of the plurality of sub-arrays of configurable units on the reconfigurable data processor;
receiving a force-quit initiation from a runtime program at an interface agent of the reconfigurable data processor, the force-quit initiation indicating that a force-quit process should be initiated on the first sub-array of configurable units without impacting the execution of the second program on the second sub-array of configurable units;
sending a force-quit signal from the interface agent to a force-quit controller for the first sub-array; and
resetting configurable units in the first sub-array of configurable units in response to the force-quit signal which stops the execution of the first program while the execution of the second program on the second sub-array of configurable units continues.