Integrated circuit that mitigates inductive-induced voltage overshoot
An integrated circuit (IC) includes an array of compute units and control circuitry for mitigating supply voltage overshoot. Each compute unit contributes to an aggregate time rate of change of current drawn by the IC when transitioning between processing and non-processing states. The control circuitry is configurable to stagger when each compute unit is eligible to transition from processing data to not processing data relative to other compute units, thereby limiting the negative rate of change of current through inductive loads of the IC and preventing voltage overshoot above a maximum threshold. The control circuitry may be distributed among the compute units and configured using statically reconfigurable parameters that specify the maximum number of compute units permitted to transition concurrently and the minimum number of clock cycles between successive group transitions.
1 . An integrated circuit (IC), comprising:
an array of compute units;
wherein each compute unit is configured such that, when transitioning from processing data to not processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC;
control circuitry configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from processing data to not processing data relative to when the other compute units stop processing data to mitigate supply voltage overshoot caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.
2 . The IC of claim 1 ,
wherein each of the compute units comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units.
3 . The IC of claim 2 ,
wherein the integrated circuit further comprises switches that connect the compute units;
wherein each of the switches comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units and among the switches.
4 . The IC of claim 2 ,
wherein the integrated circuit further comprises memory units that buffer data to and/or from the compute units;
wherein each of the memory units comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units and among the memory units.
5 . The IC of claim 1 , further comprising:
configuration storage statically reconfigurable with configuration data usable by the control circuitry to control when each of the compute units is eligible to transition from processing data to not processing data relative to when the other compute units stop processing data to mitigate the supply voltage overshoot.
6 . The IC of claim 1 ,
wherein the control circuitry is configurable to control the compute units such that no more than a statically reconfigurable number of compute units concurrently transitions from processing data to not processing data.
7 . The IC of claim 6 ,
wherein the statically reconfigurable number of compute units is based on simulations that estimate the individual contribution made by each compute unit to the aggregate time rate of change of current drawn by the IC when transitioning from processing data to not processing data.
8 . The IC of claim 7 ,
wherein the simulations estimate the individual contribution as a time rate of change of current drawn by the individual compute unit for approximately S clock cycles beginning with a clock cycle in which the transition from processing data to not processing data occurs, wherein S is a number of pipeline stages of the individual compute unit.
9 . The IC of claim 6 ,
wherein the statically reconfigurable number of compute units is based on a clock period of the IC.
10 . The IC of claim 1 ,
wherein the control circuitry is configurable to control the compute units such that at least a statically reconfigurable number of clock cycles passes between a first clock cycle in which a group of compute units concurrently transitions from processing data to not processing data and a second clock cycle in which a temporally adjacent group of compute units concurrently transitions from processing data to not processing data.
11 . The IC of claim 1 ,
wherein the control circuitry is configurable to control the compute units such that at least a statically reconfigurable number of clock cycles passes between a first clock cycle in which a group of no more than a statically reconfigurable number of compute units concurrently transitions from processing data to not processing data and a second clock cycle in which a temporally adjacent group of no more than the statically reconfigurable number of compute units concurrently transitions from processing data to not processing data.
12 . The IC of claim 1 ,
wherein the IC comprises a dataflow architecture processor statically reconfigurable to process data according to a dataflow graph; and
wherein the compute units are statically reconfigurable to perform operations of the dataflow graph.
13 . The IC of claim 1 ,
wherein the compute units of the array are homogeneous with respect to their configurability to process data.
14 . A method, comprising:
in an integrated circuit (IC), comprising an array of compute units, wherein each compute unit is configured such that, when transitioning from processing data to not processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC:
for each compute unit of the array of compute units:
controlling, by control circuitry, when the compute unit is eligible to transition from processing data to not processing data relative to when the other compute units stop processing data to mitigate supply voltage overshoot caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.
15 . The method of claim 14 ,
wherein each of the compute units comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units.
16 . The method of claim 15 ,
wherein the integrated circuit further comprises switches that connect the compute units;
wherein each of the switches comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units and among the switches.
17 . The method of claim 15 ,
wherein the integrated circuit further comprises memory units that buffer data to and/or from the compute units;
wherein each of the memory units comprises a portion of the control circuitry such that the control circuitry is distributed among the compute units and among the memory units.
18 . The method of claim 14 , further comprising:
statically reconfiguring configuration storage of the integrated circuit with configuration data usable by the control circuitry to control when each of the compute units is eligible to transition from processing data to not processing data relative to when the other compute units stop processing data to mitigate the supply voltage overshoot.
19 . The method of claim 14 , further comprising:
controlling, by the control circuitry, the compute units such that no more than a statically reconfigurable number of compute units concurrently transitions from processing data to not processing data.
20 . The method of claim 19 ,
wherein the statically reconfigurable number of compute units is based on simulations that estimate the individual contribution made by each compute unit to the aggregate time rate of change of current drawn by the IC when transitioning from processing data to not processing data.
21 . The method of claim 20 ,
wherein the simulations estimate the individual contribution as a time rate of change of current drawn by the individual compute unit for approximately S clock cycles beginning with a clock cycle in which the transition from processing data to not processing data occurs, wherein S is a number of pipeline stages of the individual compute unit.
22 . The method of claim 19 ,
wherein the statically reconfigurable number of compute units is based on a clock period of the IC.
23 . The method of claim 14 , further comprising:
controlling, by the control circuitry, the compute units such that at least a statically reconfigurable number of clock cycles passes between a first clock cycle in which a group of compute units concurrently transitions from processing data to not processing data and a second clock cycle in which a temporally adjacent group of compute units concurrently transitions from processing data to not processing data.
24 . The method of claim 14 , further comprising:
controlling, by the control circuitry, the compute units such that at least a statically reconfigurable number of clock cycles passes between a first clock cycle in which a group of no more than a statically reconfigurable number of compute units concurrently transitions from processing data to not processing data and a second clock cycle in which a temporally adjacent group of no more than the statically reconfigurable number of compute units concurrently transitions from processing data to not processing data.
25 . The method of claim 14 ,
wherein the IC comprises a dataflow architecture processor statically reconfigurable to process data according to a dataflow graph; and
wherein the compute units are statically reconfigurable to perform operations of the dataflow graph.
26 . The method of claim 14 ,
wherein the compute units of the array are homogeneous with respect to their configurability to process data.
27 . A non-transitory computer-readable storage medium having computer program instructions stored thereon that are capable of causing or configuring an integrated circuit (IC), comprising:
an array of compute units;
wherein each compute unit is configured such that, when transitioning from processing data to not processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC;
control circuitry configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from processing data to not processing data relative to when the other compute units stop processing data to mitigate supply voltage overshoot caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.