IP Library Granted Patent US 11,848,321
Granted Patent B2
US 11,848,321 · App. 17/238,987 · Granted Dec 19, 2023

Semiconductor device for providing spike voltage protection and manufacturing method thereof

Inventors: Hong-Shyang Wu (Taipei, TW); Kuo-Ming Wu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L27/0259
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Quick Facts
Patent No.
US 11,848,321
App. No.
17/238,987
Granted
Dec 19, 2023
Kind
B2
Abstract

A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.

Claims (37)

1. A semiconductor device, comprising:

an output circuit configured to be electrically connected between a driving circuit and an external load circuit; and

a protection circuit electrically connected to the output circuit and the driving circuit, the protection circuit comprises:

a first transistor having a base electrode, a collector electrode and an emitter electrode; and

a second transistor having a base electrode, a collector electrode and an emitter electrode,

wherein the base electrode of the first transistor is electrically connected to the collector electrode of the second transistor, and wherein a first size of the emitter electrode of the first transistor is different than a second size of the emitter electrode of the second transistor.

2. The semiconductor device of claim 1 , wherein the emitter electrode of the first transistor is electrically connected to the base electrode of the second transistor.

3. The semiconductor device of claim 1 , wherein the collector electrode of the first transistor is electrically connected to the collector electrode of the second transistor.

4. The semiconductor device of claim 1 , wherein the emitter electrode of the second transistor is electrically connected to the output circuit.

5. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are NPN bipolar junction transistors (BJT).

6. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are PNP bipolar junction transistors (BJT).

7. The semiconductor device of claim 1 , wherein the base electrode of the first transistor is electrically connected to the collector electrode of the first transistor.

8. The semiconductor device of claim 1 , wherein the protection circuit further comprises a third transistor having a base electrode, a collector electrode and an emitter electrode, wherein the collector electrode of the third transistor is electrically connected to the base electrode of the first transistor.

9. The semiconductor device of claim 1 , wherein a breakdown voltage of the first and second transistors ranges approximately from 0.6V to 0.8V.

10. A semiconductor device, comprising:

an output circuit configured to be electrically connected between a driving circuit and an external load circuit;

a protection circuit electrically connected to the output circuit and the driving circuit, the protection circuit comprises:

a first quantity of transistors;

wherein collector electrodes of the first quantity of transistors are electrically connected, and a base electrode of a first transistor of the first quantity of transistors is electrically connected to a collector electrode of a second transistor of the first quantity of transistors, and wherein a first size of an emitter electrode of the first transistor of the first quantity of transistors is different than a second size of an emitter electrode of the second transistor of the first quantity of transistors.

11. The semiconductor device of claim 10 , further comprising a second quantity of transistors, wherein the collector electrodes of the second quantity of transistors are electrically connected, and a base electrode of a first transistor of the second quantity of transistors is electrically connected to a collector electrode of a second transistor of the second quantity of transistors.

12. The semiconductor device of claim 11 , wherein the first quantity is identical to the second quantity.

13. The semiconductor device of claim 11 , wherein the first quantity is different from the second quantity.

14. The semiconductor device of claim 11 , wherein the first quantity of transistors and the second quantity of transistors are arranged in parallel.

15. The semiconductor device of claim 14 , wherein the collector electrodes of the first quantity of transistors are electrically connected to the collector electrodes of the second quantity of transistors.

16. A method of manufacturing a semiconductor device, comprising:

forming a substrate;

forming a first well region in the substrate;

forming a second well region in the substrate, wherein the first well region is electrically connected to the second well region and wherein a conductivity type of the first well region is different from a conductivity type of the second well region;

forming a third well region in the substrate; and

forming a fourth well region in the substrate;

forming a fifth well region in the substrate, wherein a conductivity type of the fourth well region is different from a conductivity type of the fifth well region;

electrically connecting the second well region to the third well region.

17. The method of claim 16 , further comprising:

electrically connecting the fourth well region to the fifth well region.

18. The method of claim 16 , wherein the second well region and the third well region are electrically connected via a conductive element.

19. The method of claim 17 , wherein the fourth well region and the fifth well region are electrically connected via a conductive element.

20. The method of claim 16 , wherein a conductivity type of the second well region is different from a conductivity type of the third well region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2021
From: WU, HONG-SHYANG; WU, KUO-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 056024/0001 →
Continuity (1)
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