Memory unit partitioning solutions for reconfigurable dataflow computing systems

1. A system for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the system comprising:

a parser configured to receive and parse source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

a tensor expression extractor configured to extract the plurality of tensor indexing expressions from the source code;

a logical memory constraint generator configured to convert the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

a grouping module configured to group the plurality of logical memory indexing constraints into concurrent access groups;

a memory partitioning module configured to determine a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and

reconfigurable dataflow processor configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution;

wherein memory units in the array of memory units comprise address generators that generate, for each memory cycle, a physical address comprising a bank identifier and a bank offset;

wherein said memory units in the array of memory units are configured to respond to a specific bank identifier;

wherein the memory partitioning module is further configured to determine the memory unit partitioning solution by selecting a set of logical-to-physical mapping parameters; and

wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P.

2. A system for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the system comprising:

a parser configured to receive and parse source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

a tensor expression extractor configured to extract the plurality of tensor indexing expressions from the source code;

a logical memory constraint generator configured to convert the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

a grouping module configured to group the plurality of logical memory indexing constraints into concurrent access groups;

a memory partitioning module configured to determine a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and

reconfigurable dataflow processor configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution;

wherein memory units in the array of memory units comprise address generators that generate, for each memory cycle, a physical address comprising a bank identifier and a bank offset;

wherein said memory units in the array of memory units are configured to respond to a specific bank identifier;

wherein the memory partitioning module is further configured to determine the memory unit partitioning solution by selecting a set of logical-to-physical mapping parameters;

wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P; and

wherein selecting comprises testing legal combinations of N, B and alpha.

3. A system for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the system comprising:

a parser configured to receive and parse source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

a tensor expression extractor configured to extract the plurality of tensor indexing expressions from the source code;

a logical memory constraint generator configured to convert the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

a grouping module configured to group the plurality of logical memory indexing constraints into concurrent access groups;

a memory partitioning module configured to determine a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and

reconfigurable dataflow processor configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution;

further comprising a capacity modification module configured to perform a capacity modification to legalize the memory unit partitioning solution; and

wherein the capacity modification comprises scaling packing vector P or increasing a logical memory unit count N of a set of logical-to-physical mapping parameters.

4. A method for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the method comprising:

receiving source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

converting the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

grouping the plurality of logical memory indexing constraints into concurrent access groups;

determining a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and

accessing the array of memory units according to the memory unit partitioning solution in conjunction with executing the plurality of tensor indexing expressions with the reconfigurable dataflow processor;

wherein determining the memory unit partitioning solution comprises selecting a set of logical-to-physical mapping parameters; and

wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P.

5. A method for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the method comprising:

receiving source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

converting the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

grouping the plurality of logical memory indexing constraints into concurrent access groups;

determining a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts;

accessing the array of memory units according to the memory unit partitioning solution in conjunction with executing the plurality of tensor indexing expressions with the reconfigurable dataflow processor;

wherein determining the memory unit partitioning solution comprises selecting a set of logical-to-physical mapping parameters;

wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P; and

wherein selecting comprises testing legal combinations of N, B and alpha.

6. A method for determining and using memory unit partitioning solutions for reconfigurable dataflow computing systems, the method comprising:

receiving source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;

converting the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;

grouping the plurality of logical memory indexing constraints into concurrent access groups;

determining a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and

accessing the array of memory units according to the memory unit partitioning solution in conjunction with executing the plurality of tensor indexing expressions with the reconfigurable dataflow processor;

further comprising performing a capacity modification to legalize the memory unit partitioning solution; and

wherein the capacity modification comprises scaling a packing vector P or increasing a logical memory unit count N of a set of logical-to-physical mapping parameters.