Force quit of reconfigurable processor
A reconfigurable processor includes a plurality of sub-arrays of configurable units, each sub-array including a master address generation and coalescing unit (MAGCU) containing a force-quit controller. The force-quit controller on a MAGCU of a particular sub-array is configurable to execute a force-quit process in response to a force-quit command, including transitioning MAGCU from any current state to a force-quit wait state, starting a counter, broadcasting force-quit control signals to reset the configurable units in the particular sub-array, and de-asserting an output port of MAGCU on an interconnect among the configurable units. Upon expiration of the counter, MAGCU is configurable to assert its output onto the interconnect once its input and output buffers are empty, sample an input port from the interconnect to detect that every configurable unit in the particular sub-array has asserted its output port onto the interconnect, and send a force-quit completion interrupt.
1. A reconfigurable processor, comprising:
an array of configurable units on an integrated circuit substrate, the array including a plurality of sub-arrays of configurable units; and
a force-quit controller on a particular sub-array in the plurality of sub-arrays, configurable to receive a force-quit command, and generate force-quit control signals that reset configurable units in the particular sub-array.
2. The reconfigurable processor of claim 1 , further comprising an interface agent coupled to the force-quit controller and configured to send the force-quit command to the force-quit controller, wherein the interface agent communicates data between the array and an interface bus over a top level network, and wherein the interface bus is connected to a host processor via an interface link.
3. The reconfigurable processor of claim 2 , wherein the force-quit control signals cause a particular configurable unit of the particular sub-array that includes the force-quit controller to complete outstanding transactions on the top level network.
4. The reconfigurable processor of claim 2 , wherein the interface agent is further coupled to an interface bus and configured to receive a force-quit message written to a register in an address space of the interface bus by a runtime program running on a host processor, and send the force-quit command to the force-quit controller in response.
5. The reconfigurable processor of claim 4 , wherein the register is located in a configuration address space of the interface bus.
6. The reconfigurable processor of claim 4 , wherein the force-quit message comprises a sub-array-specific, force-quit bit sequence written to the register.
7. The reconfigurable processor of claim 6 , wherein the interface agent includes a sequence detector that detects the sub-array-specific, force-quit bit sequence from the configuration register.
8. The reconfigurable processor of claim 7 , wherein the interface agent generates the force-quit command as a strobe signal in response to the sequence detector detecting the sub-array-specific, force-quit bit sequence.
9. The reconfigurable processor of claim 8 , wherein the interface agent sends the force-quit command to the force-quit controller via a global wire.
10. The reconfigurable processor of claim 4 , wherein the force-quit message is a mask.
11. The reconfigurable processor of claim 4 , wherein the force-quit message is a mask having one bit for each sub-array in the plurality of sub-arrays.
12. The reconfigurable processor of claim 1 , wherein the force-quit controller is further configurable to broadcast the force-quit control signals to the configurable units in the particular sub-array over an array level network connected to the configurable units in the particular sub-array.
13. The reconfigurable processor of claim 1 , wherein the force-quit control signals cause the configurable units in the particular sub-array to reset their internal states.
14. The reconfigurable processor of claim 1 , wherein the force-quit control signals cause the configurable units in the particular sub-array to empty their input buffers and output buffers.
15. The reconfigurable processor of claim 1 , wherein at least one configurable unit in the particular sub-array is unresponsive to communication from a host processor.
16. A processing system, comprising:
an array of processing units;
force-quit logics coupled to the processing units, each force-quit logic configurable to:
receive a force-quit control signal, and
reset an associated processing unit in response to the force-quit control signal; and
the force-quit logics connected in an interconnect topology among the processing units, such that each force-quit logic is further configurable, in response to receiving the force-quit control signal, to:
generate a force-quit done signal to indicate completion of the reset of the associated processing unit, and
forward the force-quit done signal on the interconnect topology once a force-quit done signal from a preceding processing unit's force-quit logic on the interconnect topology is received.
17. The processing system of claim 16 , further comprising a force-quit controller configurable to broadcast force-quit control signals to the processing units, and to receive a force-quit done signal from a last processing unit's force-quit logic on the interconnect topology.
18. The processing system of claim 16 , wherein each force-quit logic is further configurable to execute a force-quit process for the associated processing unit, including:
transitioning the associated processing unit from a current state to a force-quit drain state in response to receiving the force-quit control signal;
while in the force-quit drain state:
de-asserting the force-quit done signal to the interconnect topology; and
starting a force-quit drain counter;
upon expiration of the force-quit drain counter, transitioning the associated processing unit from the force-quit drain state to a force-quit done state; and
while in the force-quit done state:
asserting the force-quit done signal to the interconnect topology in response to an input port from the interconnect topology being asserted.
19. The processing system of claim 16 , wherein the interconnect topology comprises a daisy chain.
20. The processing system of claim 16 , each processing unit in the array of processing units having a FORCE_QUIT_DONE_IN input and a FORCE_QUIT_DONE_OUT output, the FORCE_QUIT_DONE_OUT output asserted only while both FORCE_QUIT_DONE_IN and the force-quit done signal indicating the reset of the processing unit are asserted.