Performance estimation-based resource allocation for reconfigurable architectures
The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.
1. A computer-implemented method of efficiently executing an operation unit graph on a reconfigurable data processor with a target architecture that includes physical compute units and/or physical memory units, the method including:
reducing a number of the physical compute units and/or physical memory units of the reconfigurable data processor required to execute the operation unit graph by
receiving, from a user, architectural hints that are specific to the target architecture of the reconfigurable data processor,
wherein the architectural hints
call for fusing first operation units when executing a pattern of the first operation units on the physical compute units and/or physical memory units of the reconfigurable data processor,
specify the first operation units in the pattern as first nodes,
specify first dataflows among the first operation units in the pattern as first edges, and
direct fusion among the first operation units in the pattern;
scanning the operation unit graph to detect an instance of the pattern of the first operation units specified by the architectural hints, including
matching second nodes and second edges in the operation unit graph with the first nodes and the first edges in the architectural hints, and detecting a pattern match;
fusing operation units of the second nodes and the second edges in the operation unit graph into a consolidated operation units block, thereby producing a fused operation unit graph;
allocating a set of physical compute units and/or physical memory units of the physical compute units and/or physical memory units of the reconfigurable data processor to the fused operation unit graph; and
executing the fused operation unit graph on the reconfigurable data processor based on the allocation.
2. The computer-implemented method of claim 1 , wherein the architectural hints specify a first output operation unit in the pattern as a first output node.
3. The computer-implemented method of claim 2 , further including:
detecting the pattern matches by
matching the first output node specified by the architectural hints with a second output node in the operation unit graph, and
beginning with the second output node in the operation unit graph,
traversing the operation unit graph to determine that the second nodes and the second edges in the operation unit graph match the first nodes and the first edges in the architectural hints.
4. The computer-implemented method of claim 3 , wherein the traversal is an upward traversal.
5. The computer-implemented method of claim 1 , further including:
identifying an operation unit of the operation unit graph that is fused into the consolidated operation units block but has a dataflow to another operation unit of the operation unit graph which is outside the consolidated operation units block;
duplicating the identified operation unit and its dataflows and duplicating any other operation unit in the consolidated operation units block that provides input to the identified operation unit and its dataflows to create duplicated operation units and dataflows in the fused operation unit graph; and
based on the fused operation unit graph with the consolidated operation units block and the duplicated operation units and dataflows, performing the allocating and the executing.
6. The computer-implemented method of claim 1 , wherein the architectural hints are expressed as lists of nodes and edges that translate into a pattern graph.
7. A non-transitory computer readable storage medium impressed with computer program instructions to efficiently execute an operation unit graph on a reconfigurable data processor with a target architecture that includes physical compute units and/or physical memory units, the instructions, when executed on a processor, implement a method comprising:
reducing a number of the physical compute units and/or physical memory units of the reconfigurable data processor required to execute the operation unit graph by
receiving, from a user, architectural hints that are specific to the target architecture of the reconfigurable data processor,
wherein the architectural hints
call for fusing first operation units when executing a pattern of the first operation units on the physical compute units and/or physical memory units of the reconfigurable data processor,
specify the first operation units in the pattern as first nodes,
specify first dataflows among the first operation units in the pattern as first edges, and
direct fusion among the first operation units in the pattern;
scanning the operation unit graph to detect an instance of the pattern of the first operation units specified by the architectural hints, including
matching second nodes and second edges in the operation unit graph with the first nodes and the first edges in the architectural hints, and detecting pattern matches;
fusing operation units of the second nodes and the second edges in the operation unit graph into a consolidated operation units block, thereby producing a fused operation unit graph;
allocating a set of physical compute units and/or physical memory units of the physical compute units and/or physical memory units of the reconfigurable data processor to the fused operation unit graph; and
executing the fused operation unit graph on the reconfigurable data processor based on the allocation.
8. The non-transitory computer readable storage medium of claim 7 , wherein the architectural hints specify a first output operation unit in the pattern as a first output node.
9. The non-transitory computer readable storage medium of claim 8 , implementing the method further comprising:
detecting the pattern matches by
matching the first output node specified by the architectural hints with a second output node in the operation unit graph, and
beginning with the second output node in the operation unit graph,
traversing the operation unit graph to determine that the second nodes and the second edges in the operation unit graph match the first nodes and the first edges in the architectural hints.
10. The non-transitory computer readable storage medium of claim 9 , wherein the traversal is an upward traversal.
11. The non-transitory computer readable storage medium of claim 7 , implementing the method further comprising:
identifying an operation unit of the operation unit graph that is fused into the consolidated operation units block but has a dataflow to another operation unit of the operation unit graph which is outside the consolidated operation units block;
duplicating the identified operation unit and its dataflows and duplicating any other operation unit in the consolidated operation units block that provides input to the identified operation unit and its dataflows to create duplicated operation units and dataflows in the fused operation unit graph; and
based on the fused operation unit graph with the consolidated operation units block and the duplicated operation units and dataflows, performing the allocating and the executing.
12. The non-transitory computer readable storage medium of claim 7 , wherein the architectural hints are expressed as lists of nodes and edges that translate into a pattern graph.
13. A system including one or more processors coupled to memory, the memory loaded with computer instructions to efficiently execute an operation unit graph on a reconfigurable data processor with a target architecture that includes physical compute units and/or physical memory units, the instructions, when executed on the processors, implement actions comprising:
reducing a number of the physical compute units and/or physical memory units of the reconfigurable data processor required to execute the operation unit graph by
receiving, from a user, architectural hints that are specific to the target architecture of the reconfigurable data processor,
wherein the architectural hints
call for fusing first operation units when executing a pattern of the first operation units on the physical compute units and/or physical memory units of the reconfigurable data processor,
specify the first operation units in the pattern as first nodes,
specify first dataflows among the first operation units in the pattern as first edges, and
direct fusion among the first operation units in the pattern;
scanning the operation unit graph to detect an instance of the pattern of the first operation units specified by the architectural hints, including
matching second nodes and second edges in the operation unit graph with the first nodes and the first edges in the architectural hints, and detecting a pattern match;
fusing operation units of the second nodes and the second edges in the operation unit graph into a consolidated operation units block, thereby producing a fused operation unit graph;
allocating a set of physical compute units and/or physical memory units of the physical compute units and/or physical memory units of the reconfigurable data processor to the fused operation unit graph; and
executing the fused operation unit graph on the reconfigurable data processor based on the allocation.
14. The system of claim 13 , wherein the architectural hints specify a first output operation unit in the pattern as a first output node.
15. The system of claim 14 , implementing actions further comprising:
detecting the pattern matches by
matching the first output node specified by the architectural hints with a second output node in the operation unit graph, and
beginning with the second output node in the operation unit graph,
traversing the operation unit graph to determine that the second nodes and the second edges in the operation unit graph match the first nodes and the first edges in the architectural hints.
16. The system of claim 15 , wherein the traversal is an upward traversal.
17. The system of claim 13 , implementing actions further comprising:
identifying an operation unit of the operation unit graph that is fused into the consolidated operation units block but has a dataflow to another operation unit of the operation unit graph which is outside the consolidated operation units block;
duplicating the identified operation unit and its dataflows and duplicating any other operation unit in the consolidated operation units block that provides input to the identified operation unit and its dataflows to create duplicated operation units and dataflows in the fused operation unit graph; and
based on the fused operation unit graph with the consolidated operation units block and the duplicated operation units and dataflows, performing the allocating and the executing.
18. The system of claim 13 , wherein the architectural hints are expressed as lists of nodes and edges that translate into a pattern graph.