IP Library Patent Application 17824830
Patent Application
App. No. 17/824,830

Matrix Multiplication on Coarse-grained Computing Grids

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Quick Facts
Patent No.
US None
App. No.
17/824,830
Abstract

A method for multiplying matrices in a coarse-grained computing grid includes assigning each compute unit c of C compute units to a unique submatrix R c of a result matrix R, wherein the C compute units are arranged in a 2D computing grid, configuring one or more source memory units to provide relevant matrix A data and matrix B data to the C compute units via a plurality of packets, configuring each compute unit c to produce the unique submatrix R c and send the unique submatrix R c to one or more desired memory units. The method also includes initiating data flow in the computing grid to produce the result matrix R within the desired memory units. To reduce packet traffic, Matrix B data corresponding to a column of compute units may be narrow-casted to each column of compute units. A corresponding system and computer-readable medium are also disclosed herein.

Claims (36)

1 . A system for multiplying matrices A and B and producing a result matrix R in a coarse-grained computing grid, the system comprising:

an RDU comprising a computing grid, the computing grid comprising C compute units arranged in a 2D grid comprising m logical rows and n logical columns;

an assignment module for assigning each compute unit c of C compute units to a unique submatrix R c of a result matrix R comprising M rows and N columns;

a memory unit configuration module for generating memory unit configuration information that enables one or more source memory units to provide relevant matrix A data and matrix B data to the C compute units via a plurality of packets;

a compute unit configuration module for generating compute unit configuration information that enables each compute unit c to produce the unique submatrix R c and send the unique submatrix R c to one or more desired memory units;

an RDU control module for communicating the memory unit configuration information and the compute unit configuration information to the RDU and initiating data flow in the computing grid to produce the result matrix R within the desired memory units; and

wherein providing matrix B data to the C compute units comprises narrowcasting packets to each column of compute units in the computing grid, wherein the narrow-casted packets comprise matrix B data corresponding to the column of compute units.

2 . The system of claim 1 , wherein the compute unit configuration module configures each compute unit to send submatrix R c of the result matrix R to one or more desired memory units for the result matrix R.

3 . The system of claim 1 , wherein each compute unit c of the C compute units produces the unique submatrix R c by sequentially providing column-based vectors for matrix A to a vector bus and concurrently conducting a multiply accumulate operation for each data element of the column-based vectors.

4 . The system of claim 1 , wherein the compute units for each row of the computing grid are connected to a memory unit dedicated to that row of the computing grid.

5 . The system of claim 4 , wherein all rows of matrix A are stored in the memory unit dedicated to that row of the computing grid.

6 . The system of claim 1 , wherein the compute units of the computing grid are connected to a grid connected memory unit that provides the narrow-casted packets.

7 . The system of claim 1 , wherein a compute unit of the 2D computing grid comprises an array of arithmetic units comprising I lanes and J pipelined stages.

8 . The system of claim 7 , wherein the compute unit comprises a streaming port configurable to sequentially stream K vector packets comprising matrix A data through the I lanes of the array of arithmetic units where each vector packet of the K vector packets comprises I column-ordered data elements corresponding to I rows of matrix A data.

9 . The system of claim 8 , wherein a row connected memory unit is configurable to stream the I rows of matrix A data to the vector port via the K vector packets.

10 . The system of claim 8 , wherein the compute unit comprises a staging port configurable to receive J vector packets corresponding to J columns of matrix B data and sequentially provide a data element from each of the J vector packets to a corresponding stage of the array of compute units.

11 . The system of claim 10 , wherein the data element is concurrently provided to every arithmetic unit of the corresponding stage of the array of arithmetic units.

12 . The system of claim 10 , wherein each arithmetic unit of the array of arithmetic units is configurable to repetitively conduct a multiply-accumulate operation using a data element from the streaming port and a data element from the staging port.

13 . A method for multiplying matrices A and B and producing a result matrix R in a coarse-grained computing grid, the method comprising:

assigning each compute unit c of C compute units to a unique submatrix R c of a result matrix R comprising M rows and N columns, wherein the C compute units are arranged in a computing grid comprising m logical rows and n logical columns;

configuring one or more source memory units to provide relevant matrix A data and matrix B data to the C compute units via a plurality of packets;

configuring each compute unit c to produce the unique submatrix R c and send the unique submatrix R c to one or more desired memory units;

initiating data flow in the computing grid to produce the result matrix R within the desired memory units; and

wherein providing matrix B data to the C compute units comprises narrowcasting packets to each column of compute units in the computing grid, wherein the narrow-casted packets comprise matrix B data corresponding to the column of compute units.

14 . The method of claim 13 , further comprising configuring each compute unit to send submatrix R c of the result matrix R to one or more desired memory units for the result matrix R.

15 . The method of claim 13 , wherein the plurality of packets are vector-sized packets each comprising a vector of data elements that can be processed in parallel by a compute unit.

16 . The method of claim 13 , wherein each compute unit c of the C compute units produces the unique submatrix submatrix R c by sequentially providing column-based vectors for matrix A to a vector bus and concurrently conducting a multiply accumulate operation for each data element of the column-based vectors.

17 . The method of claim 13 , wherein the compute units for each row of the computing grid are connected to a memory unit dedicated to that row of the computing grid.

18 . The method of claim 17 , wherein all rows of matrix A are stored in the memory unit dedicated to that row of the computing grid.

19 . The method of claim 18 , further comprising providing the narrow-casted packets via a grid connected memory unit connected to each of the compute units of the computing grid.

20 . A computer readable medium having instructions encoded thereon to execute a method for multiplying matrices A and B and producing a result matrix R in a coarse-grained computing grid, the method comprising:

assigning each compute unit c of C compute units to a unique submatrix R c of a result matrix R comprising M rows and N columns, wherein the C compute units are arranged in a computing grid comprising m rows and n columns;

configuring one or more source memory units to provide relevant matrix A data and matrix B data to the C compute units via a plurality of packets;

configuring each compute unit c to produce the unique submatrix R c and send the unique submatrix R c to one or more desired memory units;

initiating data flow in the computing grid to produce the result matrix R within the desired memory units; and

wherein providing matrix B data to the C compute units comprises narrowcasting packets to each column of compute units in the computing grid, wherein the narrow-casted packets comprise matrix B data corresponding to the column of compute units.

Assignments (2)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2023
From: NATARAJA, PRAMOD; GUPTA, SITANSHU; SIVARAMAKRISHNAN, RAM; PUNJ, AJIT
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 065156/0210 →