Granted Patent B2

US 12,578,775 · App. 18/676,855 · Granted Mar 17, 2026

Inventors: Junwei Zhou (Sunnyvale, CA); Youngmoon Choi (Milpitas, CA); Jinuk Shin (San Jose, CA)

Assignee: SambaNova Systems, Inc.

G06F1/28G06F9/44505G06F1/30G06F1/3203

Abstract

Claims (55)

1 . An integrated circuit (IC), comprising:

an array of power base units (PBUs) arranged in rows and columns;

an array-level power accumulator, including:

a power estimation unit (PEU); and

two or more column power accumulators (CPAs), coupled, via dedicated wiring, with an output of a PBU in its respective column and with the PEU; and

a power clock management controller (PCMC) coupled with the array-level power accumulator;

wherein:

at least part of the CPAs is coupled with the array-level power accumulator via the dedicated wiring.

2 . The integrated circuit of claim 1 , wherein the PBU includes:

a switch;

a memory unit;

a compute unit;

a CPE coupled with the compute unit and with the dedicated wiring;

an MPE coupled with the memory unit and with the CPE; and

an SPE coupled with the MPE and the switch;

wherein the switch is coupled with at least one of the memory unit and the compute unit.

3 . The integrated circuit of claim 2 , wherein the CPE includes:

a power calculation unit;

a bit toggle monitor coupled with an input of the power calculation unit;

a configuration register coupled with an input of the power calculation unit;

an activity monitor coupled with an input of the power calculation unit;

a power lookup table (LUT) coupled with the power calculation unit; and

one or more interfaces coupled with the power calculation unit and with the dedicated wiring.

4 . The integrated circuit of claim 2 , wherein the MPE includes:

a power calculation unit;

a bit toggle monitor coupled with an input of the power calculation unit;

a configuration register coupled with an input of the power calculation unit;

a power LUT coupled with the power calculation unit; and

one or more interfaces coupled with the power calculation unit and with the dedicated wiring.

5 . The integrated circuit of claim 1 , wherein a CPA includes:

a first FIFO (first-in first-out register), configured to receive and synchronize first dynamic power estimates from a first part of a column;

a second FIFO, configured to receive and synchronize second dynamic power estimates from a second part of the column;

a third FIFO, configured to receive and synchronize accumulated dynamic power estimates from a previous column;

an adder with a first input coupled an output of the first FIFO, a second input coupled with an output of the second FIFO, and a third input coupled with an output of the third FIFO, and configured to accumulate the received and synchronized accumulated dynamic power estimates, first dynamic power estimates, and second dynamic power estimates; and

synchronization logic coupled with the first FIFO, the second FIFO, and the third FIFO, and configured to read received timestamps and control the first FIFO, the second FIFO, and the third FIFO based on the received timestamps.

6 . The integrated circuit of claim 1 , wherein the PEU includes:

a first CPA input coupled with an output of a first CPA;

a second CPA input coupled with an output of a second CPA;

a first sample circuit with an input coupled with the first CPA input;

a second sample circuit with an input coupled with the second CPA input;

an adder with a first input coupled with an output of the first sample circuit and with a second input coupled with an output of the second sample circuit;

a first averaging stage with a first-stage averaging input coupled with an output of the adder, wherein the first averaging stage is configured to calculate a mean average;

a second averaging stage with a second-stage averaging input coupled with an output of the first averaging stage, wherein the second averaging stage is configured to calculate a moving average; and

an averaging window register with an output coupled with a first-stage configuration input and with a second-stage configuration input, wherein the averaging window register is configured to be set by the PCMC.

7 . The integrated circuit of claim 1 , wherein the PCMC includes:

a PCMC data input configured to receive a power estimate from the PEU, wherein the power estimate is based on a nominal clock frequency and a nominal supply voltage;

a clock frequency input;

a frequency scale factor circuit coupled with the clock frequency input, wherein the frequency scale factor circuit is configured to output a power scaling factor based on a ratio between an actual clock frequency and the nominal clock frequency;

a supply voltage input;

a voltage scale factor circuit coupled with the supply voltage input, wherein the voltage scale factor circuit is configured to output a power scaling factor based on a ratio between an actual supply voltage and the nominal supply voltage;

a temperature input;

a leakage circuit coupled with the supply voltage input and the temperature input, wherein the leakage circuit is configured to output a leakage power estimate based on the actual supply voltage and an actual temperature;

a first multiplier with a first input coupled with the PCMC data input and a second input coupled with an output of the frequency scale factor circuit;

a second multiplier with a first input coupled with an output of the first multiplier and a second input coupled with an output of the voltage scale factor circuit; and

an adder with a first input coupled with an output of the second multiplier and a second input coupled with an output of the leakage circuit.

Assignments (2)

Continuity (3)

References Cited (20)