Skip buffer splitting

1. A computer-implemented method to transform a high-level program into configuration data for a coarse-grained reconfigurable (CGR) processor with an array of CGR units, comprising:

transforming at least a part of the high-level program into a dataflow graph that includes multiple interdependent asynchronously performing meta-pipelines, wherein at least one of the meta-pipelines includes a nested loop;

in the dataflow graph, identifying a first buffer that stores data that is passed from a producer in a first meta-pipeline stage to a consumer in a second meta-pipeline stage, wherein the first buffer has a first depth and the first depth is more than two timesteps;

determining hardware limitations associated with the array of CGR units, including one or more of a number of bytes in a memory unit, a maximum depth of a buffer, or a maximum fan-in of a buffer;

determining a lowest cost implementation topology and stage depth, based on a size of the data, the first depth, the hardware limitations, and one or more of three topologies, the three topologies including a cascaded buffer topology, a hybrid buffer topology, and a striped buffer topology;

assigning the first buffer to memory units and communication channels according to the lowest cost implementation topology and stage depth;

generating configuration data for the assigned memory units and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and

storing the configuration data in a non-transitory computer-readable storage medium.

2. The computer-implemented method of claim 1 , wherein:

the hybrid buffer topology includes multiple sections that include parallel memory units; and

the data travels from memory units in one to adjacent memory units in a next section without intervening reorder buffers.

3. The computer-implemented method of claim 1 , wherein:

determining a lowest cost implementation topology and stage depth includes calculating a cost based on a number of memory units and based on a number of times the data is written into a memory unit while traveling through the first buffer.

4. The computer-implemented method of claim 3 , wherein the cost factor includes a weight for the number of memory units and/or a weight for the number of times the data is written into a memory unit while traveling through the first buffer.

5. A non-transitory computer-readable storage medium storing computer program instructions to transform a high-level program into configuration data for a CGR processor with an array of CGR units, wherein the computer program instructions, when executed on a processor, implement a method comprising:

transforming at least a part of the high-level program into a dataflow graph that includes multiple interdependent asynchronously performing meta-pipelines, wherein at least one of the meta-pipelines includes a nested loop;

in the dataflow graph, identifying a first buffer that stores data that is passed from a producer in a first meta-pipeline stage to a consumer in a second meta-pipeline stage, wherein the first buffer has a first depth and the first depth is more than two timesteps;

determining hardware limitations associated with the array of CGR units, including one or more of a number of bytes in a memory unit, a maximum depth of a buffer, or a maximum fan-in of a buffer;

determining a lowest cost implementation topology and stage depth, based on a size of the data, the first depth, the hardware limitations, and one or more of three topologies, the three topologies including a cascaded buffer topology, a hybrid buffer topology, and a striped buffer topology;

assigning the first buffer to memory units and communication channels according to the lowest cost implementation topology and stage depth;

generating configuration data for the assigned memory units and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and

storing the configuration data in a non-transitory computer-readable storage medium.

6. A system including one or more processors coupled to a memory, the memory loaded with computer program instructions to transform a high-level program into configuration data for a CGR processor with an array of CGR units, wherein the computer program instructions, when executed on the one or more processors, implement actions comprising:

transforming at least a part of the high-level program into a dataflow graph that includes multiple interdependent asynchronously performing meta-pipelines, wherein at least one of the meta-pipelines includes a nested loop;

in the dataflow graph, identifying a first buffer that stores data that is passed from a producer in a first meta-pipeline stage to a consumer in a second meta-pipeline stage, wherein the first buffer has a first depth and the first depth is more than two timesteps;

determining hardware limitations associated with the array of CGR units, including one or more of a number of bytes in a memory unit, a maximum depth of a buffer, or a maximum fan-in of a buffer;

determining a lowest cost implementation topology and stage depth, based on a size of the data, the first depth, the hardware limitations, and one or more of three topologies, the three topologies including a cascaded buffer topology, a hybrid buffer topology, and a striped buffer topology;

assigning the first buffer to memory units and communication channels according to the lowest cost implementation topology and stage depth;

generating configuration data for the assigned memory units and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and

storing the configuration data in a non-transitory computer-readable storage medium.