IP Library Patent Application 18087125
Patent Application
App. No. 18/087,125

User Interactive Pipelining of a Computing Application Using a Buffer Pipeline Programming Interface

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Patent No.
US None
App. No.
18/087,125
Abstract

A method of pipelining execution stages of a pipelined application comprises an application execution program (AEP) utilizing a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS). In the method the AEP uses one interface of the PPI to determine buffers, among a set of pipeline buffers stored in physical memories of the BPAS, for the BPAS to execute operations a computing application using batches of application data. The AEP uses a second interface of the PPI to load data batches into pipeline buffers, and a third interface of the PPI to input the buffers to the BPAS for executing operations of the application. The AEP can use another interface of the PPI to allocate the buffers in particular physical memories of the BPAS. A computing system can comprise the AEP and BPAS, and can perform the method.

Claims (46)

1 . A method, the method comprising:

determining, by a computer-implemented Application Execution Program (AEP), using a first interface of a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS), a first buffer among a plurality of pipeline buffers of the BPAS, the plurality of pipeline buffers included in physical memories of the BPAS, the AEP comprising a computer program configured to interact, using interfaces of the PPI, with the BPAS to pipeline execution, by the BPAS, of operations of execution stages of the computing application, the AEP determining the first buffer based on first application execution parameters and based on the first buffer included in a first physical memory of the BPAS, the first buffer and the first application execution parameters associated with the BPAS executing operations of a first execution stage among the execution stages of the computing application;

loading into the first buffer, by the AEP, using a second interface of the PPI, a first data batch included among a plurality of data batches, the plurality of data batches comprising application data of the computing application;

inputting to the BPAS, by AEP, using a third interface of the PPI, the first buffer for the BPAS to execute the operations of the first execution stage using the first data batch in the first buffer;

determining, by the AEP, using the first interface of the PPI, a second buffer among the plurality of pipeline buffers, the AEP determining the second buffer based on second application execution parameters and based on the second buffer included in a second physical memory of the BPAS, the second buffer and the second application execution parameters associated with the BPAS executing operations of a second execution stage among the execution stages of the computing application;

loading into the second buffer, by the AEP, using the second interface of the PPI, a second data batch included among the plurality of data batches; and,

inputting to the BPAS, by AEP, using the third interface of the PPI, based on an execution status associated with the BPAS executing operations of the execution stages of the computing application, the second buffer for the BPAS to execute the operations of the second execution stage using the second data batch in the second buffer.

2 . The method of claim 1 , wherein the method the AEP loading the first data batch into the first buffer comprises the AEP loading the first data batch into the first buffer based on the first buffer included in a pool of buffers, among the plurality of pipeline buffers, available for the BPAS to execute the operations of the first execution stage, the first buffer included in the pool of buffers based on the first buffer released by the BPAS for reuse by the AEP.

3 . The method of claim 1 , wherein the second execution status is selected from a group comprising: a status of the BPAS having a stage processor available to execute the operations of the second execution stage and a status of the BPAS associated with the BPAS executing the operations of the first execution stage using the first data batch in the first buffer.

4 . The method of claim 1 , the method further comprising allocating, by the AEP, using a fourth interface of the PPI, based on the respective first and second application execution parameters, at least one of the first and second buffers in the respective first and second physical memories.

5 . The method of claim 1 , the method further comprising generating, by the AEP, data batches among the plurality of data batches.

6 . The method of claim 1 , wherein the first interface of the PPI comprises an interface of the PPI to select a stage buffer among the pipelined buffers, the stage buffer associated with a particular execution stage among the execution stages of the computation application.

7 . The method of claim 1 , wherein the second interface of the PPI comprises an interface of the PPI to input data elements, among the plurality of data batches, into stage buffers among the plurality of pipeline buffers, buffers among the stages buffers associated with particular execution stages among the execution stages of the computing application.

8 . The method of claim 1 , wherein the third interface of the PPI comprises an interface of the PPI to initiate the BPAS executing operations of a particular execution stage among the execution stages of the computing application.

9 . The method of claim 1 , wherein the first and second physical memories are selected from a group comprising: a physical memory of a host computing system, a physical memory of a runtime computing system of the BPAS, a physical memory of a stage processor of the BPAS, and a physical memory of a reconfigurable dataflow unit of the BPAS.

10 . The method of claim 1 , wherein application execution parameters, among the first and second application execution parameters, are selected from a group comprising: performance attributes of first hardware resources of the BPAS to execute first operations of the execution stages of the computing application; capacity attributes of second hardware resources of the BPAS to execute second operations of the execution stages of the computing application; and, topological attributes of third hardware resources of the BPAS to execute third operations of the execution stages of the computing application.

11 . A computing system, the system comprising:

a computing application comprising a plurality of execution stages;

a Buffer Pipelined Application computing System (BPAS) comprising a plurality of hardware processors; at least one physical memory, and a Pipeline Programming Interface (PPI), wherein the BPAS is configured to execute, responsive to interface of the PPI, operations of the plurality of execution stages;

a plurality of pipeline buffers included in the at least one physical memory of the BPAS; and,

an Application Execution Program (AEP), wherein the AEP comprises a computer program configured to:

determine, using a first interface of the PPI, a first buffer among the plurality of pipeline buffers, the AEP further configured to determine the first buffer based on first application execution parameters and based on the first buffer included in a first physical memory among the at least one physical memory of the BPAS, the first buffer and the first application execution parameters associated with the BPAS executing operations of a first execution stage among the execution stages of the computing application;

load into the first buffer, using a second interface of the PPI, a first data batch included among a plurality of data batches, the plurality of data batches comprising application data of the computing application;

input to the BPAS, using a third interface of the PPI, the first buffer for the BPAS to execute the operations of the first execution stage using the first data batch in the first buffer;

determine, using the first interface of the PPI, a second buffer among the plurality of pipeline buffers, the AEP further configured to determine the second buffer based on second application execution parameters and based on the second buffer included in a second physical memory among the at least one physical memory of the BPAS, the second buffer and the second application execution parameters associated with the BPAS executing operations of a second execution stage among the execution stages of the computing application;

load into the second buffer, using the second interface of the PPI, a second data batch included among the plurality of data batches; and,

input to the BPAS, using the third interface of the PPI, based on an execution status associated with the BPAS executing operations of the execution stages of the computing application, the second buffer for the BPAS to execute the operations of the second execution stage using the second data batch in the second buffer.

12 . The computing system of claim 11 , wherein the AEP configured to load the first data batch into the first buffer comprises the AEP further configured to load the first data batch into the first buffer based on the first buffer included in a pool of buffers, among the plurality of pipeline buffers, available for the BPAS to execute the operations of the first execution stage, the first buffer included in the pool of buffers based on the first buffer released by the BPAS for reuse by the AEP.

13 . The computing system of claim 11 , wherein the second execution status is selected from a group comprising: a status of the BPAS having a stage processor available to execute the operations of the second execution stage and a status of the BPAS associated with the BPAS executing the operations of the first execution stage using the first data batch in the first buffer.

14 . The computing system of claim 11 , wherein the AEP is further configured to allocate, using a fourth interface of the PPI, based on the respective first and second application execution parameters, at least one of the first and second buffers in the respective first and second physical memories.

15 . The computing system of claim 11 , wherein the AEP is further configured to generate data batches among the plurality of data batches.

16 . The computing system of claim 11 , wherein the first interface of the PPI comprises an interface of the PPI to select a stage buffer among the pipelined buffers, the stage buffer associated with a particular execution stage among the execution stages of the computation application.

17 . The computing system of claim 11 , wherein the second interface of the PPI comprises an interface of the PPI to input data elements, among the plurality of data batches, into stage buffers the plurality of pipeline buffers, buffers among the stages buffers associated with particular execution stages among the execution stages of the computing application.

18 . The computing system of claim 11 , wherein the third interface of the PPI comprises an interface of the PPI to initiate the BPAS executing operations of a particular execution stage among the execution stages of the computing application.

19 . The computing system of claim 11 , wherein the at least one physical memory of the BPAS is selected from a group comprising: a physical memory of a host computing system, a physical memory of a runtime computing system of the BPAS, a physical memory of a stage processor of the BPAS, and a physical memory of a reconfigurable dataflow unit of the BPAS.

20 . The computing system of claim 11 , wherein application execution parameters, among the first and second application execution parameters, are selected from a group comprising: performance attributes of first hardware resources of the BPAS to execute operations of the execution stages of the computing application; capacity attributes of second hardware resources of the BPAS to execute the operations of the execution stages of the computing application; and, topological attributes of third hardware resources of the BPAS to execute the operations of the execution stages of the computing application, wherein the first, second, and third hardware resources of the BPAS comprise at least one of a processor among the plurality of hardware processors of the BPAS and a physical memory among the at least one physical memory of the BPAS.

21 . The computing system of claim 11 , wherein the AEP comprises a computer program executable on processors among the plurality of hardware processors of the BPAS.

22 . A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the program instructions comprise program instructions of an Application Execution Program (AEP) configured to interact with a Buffer Pipelined Application computing System (BPAS), using interfaces of a Pipeline Programming Interface (PPI) of the BPAS, to pipeline execution, by the BPAS, of operations of execution stages of a computing application; and,

wherein the program instructions are executable by at least one processor to cause the at least one processor to:

determine, using a first interface of the PPI, a first buffer among a plurality of pipeline buffers of the BPAS, the plurality of pipeline buffers included in physical memories of the BPAS, the AEP comprising a computer program configured to interact, using interfaces of the PPI, with the BPAS, the programming instruction executable by the at least one processor to further cause the at least one processor to determine the first buffer based on first application execution parameters and based on the first buffer included in a first physical memory of the BPAS, the first buffer and the first application execution parameters associated with the BPAS executing operations of a first execution stage among the execution stages of the computing application;

load into the first buffer, using a second interface of the PPI, a first data batch included among a plurality of data batches, the plurality of data batches comprising application data of the computing application;

input to the BPAS, using a third interface of the PPI, the first buffer for the BPAS to execute the operations of the first execution stage using the first data batch in the first buffer;

determine, using the first interface of the PPI, a second buffer among the plurality of pipeline buffers, the programming instruction executable by the at least one processor to further cause the at least one processor to determine the second buffer based on second application execution parameters and based on the second buffer included in a second physical memory of the BPAS, the second buffer and the second application execution parameters associated with the BPAS executing operations of a second execution stage among the execution stages of the computing application;

load into the second buffer, using the second interface of the PPI, a second data batch included among the plurality of data batches; and,

input to the BPAS, using the third interface of the PPI, based on an execution status associated with the BPAS executing operations of the execution stages of the computing application, the second buffer for the BPAS to execute the operations of the second execution stage using the second data batch in the second buffer.

23 . The computer program product of claim 22 , wherein the program instructions are executable by at least one processor to further cause the at least one processor to allocate, using a fourth interface of the PPI, based on the respective first and second application execution parameters, at least one of the first and second buffers in the respective first and second physical memories.

Assignments (2)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 18, 2025
From: SAMBANOVA SYSTEMS, INC.
To: SILICON VALLEY BANK, A DIVISION OF FIRST-CITIZENS BANK & TRUST COMPANY, AS AGENT
Reel/Frame 070892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2023
From: POLZIN, JOSHUA; TURLIK, CONRAD ALEXANDER; GOEL, ARNAV; ZHENG, QI; WILSON, MARAN; SANGHVI, NEAL
To: SAMBANOVA SYSTEMS, INC.
Reel/Frame 062486/0178 →