Memory unit partitioning for reconfigurable dataflow computers
A system and method for memory unit partitioning for reconfigurable dataflow computing systems includes a parser that receives and parses source code for a reconfigurable dataflow processor, a tensor expression extractor that extracts tensor indexing expressions from the source code, a logical memory constraint generator that converts the tensor indexing expressions to logical memory indexing constraints, a grouping module that groups the logical memory indexing constraints into concurrent access groups, and a memory partitioning module that determines a memory unit partitioning solution for each concurrent access group.
1 . A system for controlling memory unit partitioning for reconfigurable dataflow computing systems, comprising:
a parser configured to receive and parse source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;
a tensor expression extractor configured to extract the plurality of tensor indexing expressions from the source code;
a logical memory constraint generator configured to convert the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;
a grouping module configured to group the plurality of logical memory indexing constraints into concurrent access groups; and
a memory partitioning module configured to determine a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts,
wherein the reconfigurable dataflow processor is configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution,
wherein memory units in the array of memory units comprise address generators that generate, for each memory cycle, a physical address comprising a bank identifier and a bank offset,
wherein said memory units in the array of memory units are configured to respond to a specific bank identifier, and wherein the memory partitioning module is further configured to determine the memory unit partitioning solution by selecting a set of logical-to-physical mapping parameters, and
wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P.
2 . A system for providing memory unit partitioning solutions for reconfigurable dataflow computing systems, the system comprising:
a parser configured to receive and parse source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;
a tensor expression extractor configured to extract the plurality of tensor indexing expressions from the source code;
a logical memory constraint generator configured to convert the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;
a grouping module configured to group the plurality of logical memory indexing constraints into concurrent access groups; and
a memory partitioning module configured to determine a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts,
wherein the dataflow processor is configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution,
wherein memory units in the array of memory units comprise address generators that generate, for each memory cycle, a physical address comprising a bank identifier and a bank offset, and wherein said memory units in the array of memory units are configured to respond to a specific bank identifier, and
wherein the memory partitioning module is further configured to determine the memory unit partitioning solution by selecting a set of logical-to-physical mapping parameters, and wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P.
3 . The system of claim 2 , wherein the selecting comprises testing legal combinations of N, B and alpha.
4 . The system of claim 2 , further comprising a capacity modification module configured to perform a capacity modification to legalize the memory unit partitioning solution.
5 . The system of claim 4 , wherein the capacity modification comprises scaling packing vector P or increasing a logical memory unit count N of a set of logical-to-physical mapping parameters.
6 . A method for controlling memory unit partitioning solutions for reconfigurable dataflow computing systems, the method comprising:
receiving source code for a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric, the source code comprising a plurality of tensor indexing expressions;
converting the plurality of tensor indexing expressions to a plurality of logical memory indexing constraints;
grouping the plurality of logical memory indexing constraints into concurrent access groups;
determining a memory unit partitioning solution for each concurrent access group that supports the plurality of logical memory indexing constraints without concurrent usage conflicts including memory unit and memory port conflicts; and
accessing the array of memory units according to the memory unit partitioning solution in conjunction with executing the plurality of tensor indexing expressions with the reconfigurable dataflow processor,
wherein determining the memory unit partitioning solution comprises selecting a set of logical-to-physical mapping parameters, and
wherein the set of logical-to-physical mapping parameters comprise a logical memory unit count N, a blocking parameter B, a scaling vector alpha and a packing vector P.
7 . The method of claim 6 , wherein selecting comprises testing legal combinations of N, B and alpha.
8 . The method of claim 6 , wherein the capacity modification comprises scaling a packing vector P or increasing a logical memory unit count N of a set of logical-to-physical mapping parameters.
9 . The method of claim 6 , wherein the selecting comprises testing legal combinations of N, B and alpha.
10 . The method of claim 8 , wherein the set of logical-to-physical mapping parameters define a hyperplane partitioning or a parallel-piped partitioning.
11 . The method of claim 6 , wherein the array of compute units operate on vectors and the memory unit partitioning solution is vectorized.