Granted Patent B2

US 12,511,252 · App. 18/518,695 · Granted Dec 30, 2025

Inventors: Tejas Nagendra Babu Nama (Palo Alto, CA); Ruddhi Chaphekar (Palo Alto, CA); Ram Sivaramakrishnan (San Jose, CA); Raghu Prabhakar (San Jose, CA); Sumti Jairath (Palo Alto, CA); Junjue Wang (Newark, CA); Kaizhao Liang (Palo Alto, CA); Adi Fuchs (Palo Alto, CA); Matheen Musaddiq (Austin, TX); Arvind Krishna Sujeeth (Palo Alto, CA)

Assignee: SambaNova Systems, Inc.

G06F15/7885G06F15/7839G06F16/9024G06F17/16

Abstract

Claims (71)

1 . A computer-implemented method comprising:

sectioning, using a processor, a processing graph for an application into a sequence of sections, the sequence of sections including at least a first section followed by a second section, the first section and the second section both respectively comprising one or more computational operations;

configuring the first section to generate, using a first reconfigurable processor as a part of executing the application, a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration;

configuring the processing graph to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration different than the first target tiling configuration; and

configuring the second section to generate, using a second reconfigurable processor as a part of executing the application, a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

2 . The method of claim 1 , further comprising:

saving, by the processor to a non-transitory computer-readable medium, configuration information for executing the application by the first section and the second section;

executing the first section of the application using the first reconfigurable processor; and

executing the second section of the application using the second reconfigurable processor.

3 . The method of claim 2 , further comprising:

reconfiguring the first output in the first target tiling configuration to the second input in the second input tiling configuration by:

storing a plurality of output tiles of the first output in the first target tiling configuration, with padding around the plurality of output tiles to generate a padded output, and

retiling the padded output to generate a plurality of input tiles of the second input in the second input tiling configuration.

4 . The method of claim 3 , further comprising storing the plurality of output tiles of the first output by:

storing the plurality of output tiles of the first output in a non-overlapping configuration.

5 . The method of claim 4 , further comprising retiling the padded output by:

retiling the padded output to generate the plurality of input tiles in an overlapping configuration.

6 . The method of claim 3 , wherein one or more input tiles of the plurality of input tiles of the second input have padding on one or more corresponding edges.

7 . The method of claim 3 , wherein:

a first input tile of the plurality of input tiles of the second input has padding only on a top edge and a left edge;

a second input tile of the plurality of input tiles of the second input has padding only on a top edge and a right edge;

a third input tile of the plurality of input tiles of the second input has padding only on a bottom edge and a left edge; and

a fourth input tile of the plurality of input tiles of the second input has padding only on a bottom edge and a right edge.

8 . The method of claim 7 , wherein:

a fifth input tile of the plurality of input tiles of the second input has padding only on a top edge;

a sixth input tile of the plurality of input tiles of the second input has padding only on a right edge;

a seventh input tile of the plurality of input tiles of the second input has padding only on a bottom edge;

an eighth input tile of the plurality of input tiles of the second input has padding only on a left edge; and

a ninth input tile of the plurality of input tiles of the second input does not have any padding of any of its edges.

9 . The method of claim 1 , wherein:

the first target tiling configuration tiles the first output into a first output set of non-overlapping tiles; and

the first input tiling configuration tiles the first input into a first input set of overlapping tiles.

10 . The method of claim 9 , wherein:

the first output set of non-overlapping tiles is generated by using tiles in the first input set of overlapping tiles as effective receptive fields.

11 . The method of claim 9 , wherein:

the second input tiling configuration tiles the second input into a second input set of overlapping tiles; and

the second target tiling configuration tiles the second output into a second output set of non-overlapping tiles.

12 . A non-transitory computer readable storage medium impressed with computer program instructions, the computer program instructions, when executed on a processor, implement a method comprising:

sectioning a processing graph for an application into a sequence of sections, the sequence of sections including at least a first section followed by a second section, the first section and the second section both respectively comprising one or more computational operations;

configuring the first section, using a first reconfigurable processor as a part of executing the application, to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration;

configuring the processing graph to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration different than the first target tiling configuration; and

configuring the second section to generate, using a second reconfigurable processor as a part of executing the application, a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

13 . The non-transitory computer readable storage medium of claim 12 , wherein:

the first target tiling configuration tiles the first output into a first output set of non-overlapping tiles; and

the first input tiling configuration tiles the first input into a first input set of overlapping tiles.

14 . The non-transitory computer readable storage medium of claim 13 , wherein:

the first output set of non-overlapping tiles is generated by using tiles in the first input set of overlapping tiles as effective receptive fields.

15 . The non-transitory computer readable storage medium of claim 13 , wherein:

the second input tiling configuration tiles the second input into a second input set of overlapping tiles; and

the second target tiling configuration tiles the second output into a second output set of non-overlapping tiles.

16 . The non-transitory computer readable storage medium of claim 12 , the method further comprising:

reconfiguring the first output in the first target tiling configuration to the second input in the second input tiling configuration by:

storing a plurality of output tiles of the first output in the first target tiling configuration, with padding around the plurality of output tiles to generate a padded output, and

retiling the padded output to generate a plurality of input tiles of the second input in the second input tiling configuration.

17 . The non-transitory computer readable storage medium of claim 16 , the method further comprising:

storing the plurality of output tiles of the first output in a non-overlapping configuration; and

retiling the padded output to generate the plurality of input tiles in an overlapping configuration;

wherein one or more input tiles of the plurality of input tiles of the second input have padding on one or more corresponding edges.

18 . A data processing system, comprising:

a processor; and

a compiler configured to execute on the processor and to:

section a processing graph for an application into a sequence of sections, the sequence of sections including at least a first section and a second section, the first section and the second section both respectively comprising one or more computational operations;

configure the first section to generate, using a first reconfigurable processor as a part of executing the application, a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration,

configure the processing graph to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration different than the first target tiling configuration, and

configure the second section, using a second reconfigurable processor as a part of executing the application, to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

19 . The data processing system of claim 18 , wherein:

the first target tiling configuration tiles the first output into a first output set of non-overlapping tiles; and

the first input tiling configuration tiles the first input into a first input set of overlapping tiles.

20 . The data processing system of claim 18 , the compiler further configured to:

store a plurality of output tiles of the first output in the first target tiling configuration, with padding around the plurality of output tiles to generate a padded output, and

retile the padded output to generate a plurality of input tiles of the second input in the second input tiling configuration.

Assignments (2)

Continuity (3)

References Cited (108)