IP Library › Granted Patent US 10,891,538
Granted Patent B2
US 10,891,538 · App. 15/659,371 · Granted Jan 12, 2021

Sparse convolutional neural network accelerator

Inventors: William J. Dally (Los Altos Hills, CA); Angshuman Parashar (Northborough, MA); Joel Springer Emer (Acton, MA); Stephen William Keckler (Austin, TX); Larry Robert Dennison (Mendon, MA)
Assignee: NVIDIA Corporation
G06N3/0427G06F9/3001G06F9/30018G06F9/30025G06F9/30036G06F9/3851G06F9/3887G06F17/11G06N3/0454G06N3/063G06N3/082G06F9/28G06F9/3555G06F17/16
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Quick Facts
Patent No.
US 10,891,538
App. No.
15/659,371
Filed
Jul 25, 2017
Granted
Jan 12, 2021
Kind
B2
Art Unit
2125
USPC
706/27
Abstract

A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

Claims (52)

1. A method, comprising:

receiving, by a parallel processing unit, a first instruction including a first index vector operand and a second index vector operand;

decoding, by the parallel processing unit, the first index vector operand to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array;

decoding, by the parallel processing unit, the second index vector operand to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array;

summing, by the parallel processing unit, the first coordinate sets with the second coordinate sets to produce output coordinate sets; and

converting, by the parallel processing unit, the output coordinate sets into a set of linear indices.

2. The method of claim 1 , wherein the summing comprises summing each first coordinate in the first coordinate sets with a third coordinate in the second coordinate sets to produce the coordinates of the output coordinate sets.

3. The method of claim 1 , wherein the first array is a three-dimensional array and the second array is a two-dimensional array.

4. The method of claim 1 , wherein the first array stores weight values and the second array stores activation values.

5. The method of claim 1 , wherein the first index vector encodes values that are accumulated in sequence to compute the first coordinates for each non-zero element in the first array.

6. The method of claim 1 , further comprising:

receiving, by the parallel processing unit, a second instruction including a first set of linear addresses operand and a second scalar values operand; and

summing, by the parallel processing unit, scalar values in the scalar values operand to values in a third array, each value in the third array corresponding to a linear address in the first set of linear addresses operand.

7. The method of claim 6 , wherein the first indices operand is the set of linear indices.

8. The method of claim 1 , further comprising:

receiving a second instruction including a first non-zero elements vector operand and a second non-zero elements vector operand; and

multiplying each one of the non-zero elements in the first non-zero values vector operand by every one of the non-zero elements in the second non-zero elements vector operand to produce a vector of products.

9. The method of claim 8 , wherein each of the non-zero elements in the first non-zero elements vector operand corresponds to an index in the first index vector operand and each of the non-zero elements in the second non-zero values vector operand corresponds to an index in the second index vector operand.

10. The method of claim 8 , further comprising:

receiving, by the parallel processing unit, a third instruction including a first set of linear addresses operand and a second scalar values operand, wherein the first set of linear addresses operand is the set of linear addresses and the second scalar values operand is the vector of products; and

summing, by the parallel processing unit, scalar values in the scalar values operand with partial sums in a third array, each partial sum in the third array corresponding to a linear address in the first set of linear addresses operand.

11. The method of claim 1 , further comprising, before receiving the first instruction:

receiving, by the parallel processing unit, a second instruction including a first scalar values operand;

generating a vector of non-zero elements including only values in the first scalar values operand that are not equal to zero; and

generating a vector of indices comprising positions within the second array, wherein each index in the vector of indices is associated with a non-zero element in the vector of non-zero elements.

12. The method of claim 11 , wherein the second indices operand is the vector of indices.

13. A processor, comprising:

parallel processing units configured to:

receive a first instruction including a first index vector operand and a second index vector operand;

decode the first index vector operand to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array;

decode the second index vector operand to produce second coordinate sets for a second array, each second coordinate set including at least the first coordinate and the second coordinate of a position of a non-zero element in the second array;

sum the first coordinate sets with the second coordinate sets to produce output coordinate sets; and

convert the output coordinate sets into a set of linear indices.

14. The processor of claim 13 , wherein the parallel processing units are further configured to sum each first coordinate in the first coordinate sets with a third coordinate in the second coordinate sets to produce the coordinates of the output coordinate sets.

15. The processor of claim 13 , wherein the first index vector encodes values that are accumulated in sequence to compute the first coordinates for each non-zero element in the first array.

16. The processor of claim 13 , the parallel processing units are further configured to:

receive a second instruction including a first set of linear addresses operand and a second scalar values operand; and

sum scalar values in the scalar values operand to values in a third array, each value in the third array corresponding to a linear address in the first set of linear addresses operand.

17. The processor of claim 16 , wherein the first indices operand is the set of linear indices.

18. The processor of claim 13 , the parallel processing units are further configured to:

receive a second instruction including a first non-zero elements vector operand and a second non-zero elements vector operand; and

multiply each one of the non-zero elements in the first non-zero values vector operand by every one of the non-zero elements in the second non-zero elements vector operand to produce a vector of products.

19. The processor of claim 13 , the parallel processing units are further configured to, before receiving the first instruction:

receive a second instruction including a first scalar values operand;

generate a vector of non-zero elements including only values in the first scalar values operand that are not equal to zero; and

generate a vector of indices comprising positions within the second array, wherein each index in the vector of indices is associated with a non-zero element in the vector of non-zero elements.

20. A non-transitory, computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

receiving a first instruction including a first index vector operand and a second index vector operand;

decoding the first index vector operand to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array;

decoding the second index vector operand to produce second coordinate sets for a second array, each second coordinate set including at least the first coordinate and the second coordinate of a position of a non-zero element in the second array;

summing the first coordinate sets with the second coordinate sets to produce output coordinate sets; and

converting the output coordinate sets into a set of linear indices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2018
From: DALLY, WILLIAM J.; PARASHAR, ANGSHUMAN; EMER, JOEL SPRINGER; KECKLER, STEPHEN WILLIAM; DENNISON, LARRY ROBERT
To: NVIDIA CORPORATION
Reel/Frame 044539/0539 →
Continuity (4)
Continuation In Part 15458799 · Mar 14, 2017
Continuation In Part 15458837 · Mar 14, 2017
Provisional Application 62373919 · Aug 11, 2016
Related Publication 20180046900A1 · Feb 15, 2018
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