Compute optimizations for neural networks
One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
1. A compute apparatus comprising:
a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network; and
an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the one-bit weight to generate an intermediate product, the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register, and the multiplication operation comprises a fused operation including an exclusive not OR (XNOR) operation and a population count operation.
2. The compute apparatus as in claim 1 , wherein the multiplier includes first circuitry to perform an XNOR operation and second circuitry to perform a population count operation on output of the first circuitry.
3. The compute apparatus as in claim 2 , wherein the multiplier includes an intermediate register to store output from the second circuitry.
4. The compute apparatus as in claim 1 , wherein the one-bit weight is a bipolar binary weight that represents a weight value of one of positive one and negative one.
5. The compute apparatus as in claim 4 , wherein the bipolar binary weight represents a weight value of negative one as a binary zero.
6. The compute apparatus as in claim 4 , wherein the value of the bipolar binary weight is referenced via an index into a multi-bit register.
7. The compute apparatus as in claim 1 , additionally including an output register to store an output value of the single instruction.
8. The compute apparatus as in claim 1 , wherein the multi-bit input value has a power of two number of bits.
9. A method comprising:
decoding a single instruction specifying multiple operands, the multiple operands including a multi-bit input value and a one-bit weight associated with a neural network;
issuing the single instruction for execution within a compute unit of a general-purpose graphics processing unit; and
responsive to the execution of the single instruction, generating a result by performing a multiplication operation on the multi-bit input value based on the one-bit weight to generate an intermediate product and updating a value stored in an accumulator register by adding the intermediate product to the value stored in the accumulator register, the multiplication operation comprising a fused operation including an exclusive not OR (XNOR) operation and a population count operation.
10. The method as in claim 9 , wherein the multiplier includes first circuitry to perform an XNOR operation and second circuitry to perform a population count operation on output of the first circuitry.
11. The method as in claim 10 , wherein the multiplier includes an intermediate register and the method additionally comprising storing output from the second circuitry to the intermediate register.
12. The method as in claim 9 , wherein the one-bit weight is a bipolar binary weight that represents a weight value of one of positive one and negative one.
13. The method as in claim 12 , wherein the bipolar binary weight represents a weight value of negative one as a binary zero.
14. The method as in claim 13 , wherein the value of the bipolar binary weight is referenced via an index into a multi-bit register.
15. The method as in claim 13 , wherein the multi-bit input value has a power of two number of bits.
16. A data processing system comprising:
a general-purpose graphics processing unit comprising:
a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, and
an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the one-bit weight to generate an intermediate product, the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register, and the multiplication operation comprises a fused operation including an exclusive not OR (XNOR) operation and a population count operation; and
a memory coupled with the general-purpose graphics processing unit.
17. The data processing system as in claim 16 , wherein the multiplier includes first circuitry to perform an XNOR operation and second circuitry to perform a population count operation on output of the first circuitry.
18. The data processing system as in claim 17 , wherein the multiplier includes an intermediate register to store output from the second circuitry.
19. The data processing system as in claim 16 , wherein the one-bit weight is a bipolar binary weight that represents a weight value of one of positive one and negative one, the bipolar binary weight represents a weight value of negative one as a binary zero, and the value of the bipolar binary weight is referenced via an index into a multi-bit register.
20. The data processing system as in claim 19 , wherein the multi-bit input value has a power of two number of bits.