Compute optimizations for neural networks using ternary weight
One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
1. A compute apparatus comprising:
a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network, wherein the ternary weight represents a weight value of one of positive one, zero, and negative one; and
an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
2. The compute apparatus as in claim 1 , wherein the weight value is referenced via an index into a multi-bit register and the ternary weight is one of multiple weights within the multi-bit register.
3. The compute apparatus as in claim 2 , wherein the ternary weight is a two-bit value.
4. The compute apparatus as in claim 3 , wherein the multiplier includes a multiplexer to select between the multi-bit input value and a zero value based on an indexed weight bit of the ternary weight value.
5. The compute apparatus as in claim 3 , wherein the multiplier includes a sign flip unit to generate the intermediate product, the sign flip unit to flip the sign of the multi-bit input value for a ternary weight value of negative one and pass through the multi-bit input value for a ternary weight value of positive one.
6. The compute apparatus as in claim 5 , wherein the sign flip unit to flip the sign of the multi-bit input value based on an indexed weight bit of the ternary weight value.
7. The compute apparatus as in claim 1 , additionally including an output register to store an output value of the single instruction.
8. The compute apparatus as in claim 1 , wherein the multi-bit input value has a power of two number of bits.
9. A method comprising:
decoding a single instruction specifying multiple operands, the operands including a multi-bit input value and a ternary weight associated with a neural network, wherein the ternary weight represents a weight value of one of positive one, zero, and negative one;
issuing the single instruction for execution within a compute unit of a general-purpose graphics processing unit; and
responsive to the execution of the single instruction, generating a result by performing a multiplication operation on the multi-bit input value based on the ternary weight to generate an intermediate product and updating a value stored in an accumulator register by adding the intermediate product to the value stored in the accumulator register.
10. The method as in claim 9 , wherein the weight value is referenced via an index into a multi-bit register and the ternary weight is one of multiple weights within the multi-bit register.
11. The method as in claim 10 , wherein the ternary weight is a two-bit value.
12. The method as in claim 11 , additionally comprising generating the intermediate product via a sign flip unit, wherein the sign flip unit is to flip the sign of the multi-bit input value for a ternary weight value of negative one and pass through the multi-bit input value for a ternary weight value of positive one.
13. The method as in claim 12 , wherein the ternary weight represents a weight value of negative one as a binary zero.
14. The method as in claim 13 , wherein the value of the ternary weight is referenced via an index into a multi-bit register.
15. The method as in claim 13 , wherein the multi-bit input value has a power of two number of bits.
16. A data processing system comprising:
a general-purpose graphics processing unit comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network, an arithmetic logic unit including a multiplier, an adder, and an accumulator register, wherein to execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input value based on the ternary weight to generate an intermediate product, the ternary weight represents a weight value of one of positive one, zero, and negative one, and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register; and
a memory coupled with the general-purpose graphics processing unit.
17. The data processing system as in claim 16 , wherein the weight value is referenced via an index into a multi-bit register and the ternary weight is one of multiple weights within the multi-bit register.
18. The data processing system as in claim 17 , wherein the multiplier includes a sign flip unit to generate the intermediate product, the sign flip unit to flip the sign of the multi-bit input value for a ternary weight value of negative one and pass through the multi-bit input value for a ternary weight value of positive one.
19. The data processing system as in claim 18 , wherein the ternary weight represents a weight value of negative one as a binary zero.
20. The data processing system as in claim 19 , wherein the multi-bit input value has a power of two number of bits.