Sparse optimizations for a matrix accelerator architecture
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.
1. A graphics processor comprising:
a processing cluster including a plurality of processing resources that are communicatively coupled via a data interconnect, a processing resource of the plurality of processing resources including:
first circuitry to execute instructions; and
second circuitry to detect a zero value data element within output generated by the first circuitry, the output including a plurality of data elements, generate metadata to indicate a location of the zero value data element within the plurality of data elements, and compress the plurality of data elements based at least in part on the metadata, the metadata including a bitfield having a plurality of bits that correspond with the plurality of data elements.
2. The graphics processor of claim 1 , the processing resource comprising third circuitry to compress the plurality of data elements based at least in part on the metadata on behalf of the second circuitry.
3. The graphics processor of claim 2 , the processing resource including a first destination register to store the output generated by the first circuitry.
4. The graphics processor of claim 3 , wherein the second circuitry to detect a zero value element within the first destination register and generate the metadata to indicate the location of the zero value element within the output.
5. The graphics processor of claim 4 , the third circuitry to write the output to a second destination register after generation of the metadata.
6. The graphics processor of claim 5 , wherein the first destination register is a temporary destination register.
7. The graphics processor of claim 1 , the first circuitry including a matrix accelerator to accelerate a matrix operation indicated by the instructions.
8. The graphics processor of claim 7 , wherein the matrix accelerator includes a plurality of processing elements.
9. The graphics processor of claim 8 , wherein the plurality of processing elements includes a systolic array of processing elements.
10. A method comprising:
on a graphics processor including a matrix accelerator:
generating output data based on a matrix operation performed by the matrix accelerator;
detecting, via zero detection circuitry, a zero value data element within a plurality of data elements within the output data; and
generating metadata to indicate a location of the zero value data element within the plurality of data elements, the metadata including a bitfield having a plurality of bits that correspond with the plurality of data elements.
11. The method of claim 10 , comprising:
writing the plurality of data elements of the output data to a first destination register;
detecting the zero value data element within the plurality of data elements within the first destination register; and
writing the plurality of data elements to a second destination register.
12. The method of claim 11 , comprising compressing the plurality of data elements within the second destination register and writing a compressed version of the plurality of data elements to a cache memory.
13. The method of claim 12 , the compressed version of the plurality of data elements including only non-zero value data elements.
14. A data processing system comprising:
a memory device; and
a graphics processor coupled with the memory device, the graphics processor comprising:
a processing cluster including a plurality of processing resources that are communicatively coupled via a data interconnect, a processing resource of the plurality of processing resources including:
first circuitry to execute instructions; and
second circuitry to detect a zero value data element within output generated by the first circuitry, the output including a plurality of data elements, generate metadata to indicate a location of the zero value data element within the plurality of data elements, and compress the plurality of data elements based at least in part on the metadata, the metadata including a bitfield having a plurality of bits that correspond with the plurality of data elements.
15. The data processing system of claim 14 , the processing resource comprising third circuitry to compress the plurality of data elements based at least in part on the metadata on behalf of the second circuitry.
16. The data processing system of claim 15 , the processing resource including a first destination register to store the output generated by the first circuitry.
17. The data processing system of claim 16 , wherein the second circuitry to detect a zero value element within the first destination register and generate the metadata to indicate the location of the zero value element within the output.
18. The data processing system of claim 17 , the third circuitry to write the output to a second destination register after generation of the metadata, wherein the first destination register is a temporary destination register.
19. The data processing system of claim 14 , the first circuitry including a matrix accelerator to accelerate a matrix operation indicated by the instructions.
20. The data processing system of claim 19 , wherein the matrix accelerator includes a plurality of processing elements.