System and method for sparse matrix vector multiplication processing
Systems and methods for sparse matrix vector multiplication (SpMV) are disclosed. The systems and methods include a novel streaming reduction architecture for floating point accumulation and a novel on-chip cache design optimized for streaming compressed sparse row (CSR) matrices. The present disclosure is also directed to implementation of the reduction circuit and/or processing elements for SpMV processing into a personality for the Convey HC-1 computing device.
1. A processing element configured for sparse matrix-vector multiplication (SpMV) processing, comprising:
a vector cache storing a subset of input vector data;
a shifter configured to receive matrix data and provide serial output matrix values;
a multiply accumulator configured to compute a dot product value from the matrix data and the input vector data, the multiply accumulator comprising a reduction circuit having an input configured to receive an incoming value of an accumulation set of the matrix data, the incoming value having an associated accumulation set id, the reduction circuit further comprising an adder configured to sum input values provided to the adder and provide the summed value to an adder output, at least one buffer in operable communication with the input and the adder output, the at least one buffer configured to provide a buffered value to the adder, the reduction circuit further comprising a plurality of data paths arranged to selectively deliver one or more of the incoming value, the buffered value, and the summed value to the adder and to the at least one buffer; and
a controller configured to control delivery of the incoming value, the buffered value, and the summed value to the adder or to the at least one buffer based on an accumulation set id associated with one or more of the incoming value, the buffered value and the summed value.
2. The processing element of claim 1 , wherein the multiply accumulator is configured to output a computed dot product value and associated accumulation set id for the computed dot product value for a row in the matrix data.
3. The processing element of claim 1 , wherein the multiply accumulator further comprises a multiplier configured to multiply matrix data associated with the accumulation set and the input vector data to provide the incoming value to the reduction circuit.
4. The processing element of claim 1 , wherein the vector cache is configured to receive the subset of vector data from a memory device storing the vector data.
5. The processing element of claim 1 , wherein the processing element is one of a plurality of processing elements,
6. The processing element of claim 5 , wherein each of the plurality of processing elements is configured to receive matrix data from a common matrix cache.
7. The processing element of claim 1 , wherein the processing element is implemented using one or more field programmable gate arrays.
8. The processing element of claim 7 , wherein the processing element is implemented as a personality for the Convey HC-1 computing device.