Compute optimizations for low precision machine learning operations

1. An accelerator on a multi-chip module, the accelerator comprising:

a memory stack including multiple memory dies; and

a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction, the at least one single instruction to accelerate a linear algebra subprogram associated with a machine learning framework;

the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions, the floating-point operation a two-dimensional matrix multiply and accumulate operation;

wherein at least a portion of the plurality of multiprocessors include a mixed precision core, the mixed precision core to execute a thread of the at least one single instruction, the mixed precision core including a floating-point unit to perform a first operation of the thread at a first precision and a second operation of the thread at a second precision; and

wherein the first operation is a multiply having at least one 16-bit floating-point input and the second operation is an accumulate having a 32-bit floating-point input.

2. The accelerator as in claim 1 , the memory stack including high bandwidth memory.

3. The accelerator as in claim 1 , wherein the memory stack is located on a same physical package as the GPU.

4. The accelerator as in claim 1 , the mixed precision core to perform the first operation at a 16-bit precision and the second operation at a 32-bit precision.

5. The accelerator as in claim 1 , wherein, the first operation has two or more 16-bit floating-point inputs.

6. The accelerator as in claim 1 , the mixed precision core configurable to output a 16-bit floating-point value from the two-dimensional matrix multiply and accumulate operation.

7. A method of accelerating a machine-learning operation, the method comprising:

decoding a single instruction on a graphics processing unit (GPU), the GPU having a single instruction, multiple thread (SIMT) architecture, the GPU coupled with a memory stack via one or more memory controllers; and

executing the single instruction via one or more multiprocessors within the GPU, the single instruction to cause at least a portion of the GPU to perform a two-dimensional matrix multiply and accumulate operation to accelerate a linear algebra subprogram associated with a machine learning framework, wherein executing the single instruction includes executing a thread of the single instruction on a mixed precision core of the one or more multiprocessors, the mixed precision core including a floating-point unit to perform a first operation of the thread at a first precision and a second operation of the thread at a second precision, wherein the first operation is a multiply having at least one 16-bit floating-point input and the second operation is an accumulate having a 32-bit floating-point input.

8. The method as in claim 7 , additionally comprising performing multiple operations on input using the mixed precision core to generate a two-dimensional output matrix and storing the two-dimensional output matrix to the memory stack via the one or more memory controllers.

9. The method as in claim 8 , wherein the memory stack includes high bandwidth memory and is located on a same physical package as the GPU.

10. The method as in claim 7 , wherein the first precision is a 16-bit precision and the second precision is a 32-bit precision.

11. The method as in claim 7 , additionally comprising generating a 16-bit floating-point output of the two-dimensional matrix multiply and accumulate operation.

12. A data processing system comprising:

a memory stack including multiple memory dies, the memory stack including high bandwidth memory; and

a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, wherein at least a portion of the plurality of multiprocessors include a mixed precision core, the mixed precision core to execute a thread of at least one single instruction, the at least one single instruction to accelerate a linear algebra subprogram associated with a machine learning framework, the mixed precision core including a floating-point unit to perform a first operation of the thread at a first precision and a second operation of the thread at a second precision; and

wherein the at least one single instruction is to cause the mixed precision core to perform a thread of a two-dimensional matrix multiply and accumulate floating-point operation on input having differing precisions, the two-dimensional matrix multiply and accumulate operation including the first operation and the second operation, the first operation a multiply having at least one 16-bit floating-point input and the second operation an accumulate having a 32-bit floating-point input.

13. The data processing system as in claim 12 , the memory stack located on a same physical package as the GPU.

14. The data processing system as in claim 12 , the mixed precision core to perform the first operation at a 16-bit precision and the second operation at a 32-bit precision.

15. The data processing system as in claim 14 , wherein, the first operation has two or more 16-bit floating-point inputs.

16. The data processing system as in claim 12 , the mixed precision core configurable to output a 16-bit floating-point value from the two-dimensional matrix multiply and accumulate operation.