Performance-driven cache line memory access

1. A method, comprising:

receiving, by a memory controller of a data processing system, a request for a cache line;

dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request;

placing the low priority data request into a low priority queue;

servicing the high priority data request;

delaying servicing of the low priority data request until a low priority condition has been satisfied; and

responsive to receiving a sector address request corresponding to the low priority data request, transferring the low priority data request to a high priority queue.

2. The method of claim 1 , further comprising:

initiating a timer; and

responsive to expiration of the timer, servicing the low priority data request.

3. The method of claim 1 , further comprising:

determining bus utilization; and

responsive to the bus utilization being below a threshold, servicing the low priority data request.

4. The method of claim 1 , further comprising,

responsive to a processor core cancelling the low priority data request, removing the low priority data request from the queue.

5. The method of claim 1 , further comprising,

responsive to receiving a castout request corresponding to an address of the low priority data request, removing the low priority data request from the queue and writing data corresponding to the address to a memory.

6. The method of claim 5 , further comprising:

placing the high priority data request into the high priority queue; and

servicing requests from the high priority queue before servicing requests from the low priority queue.