Increased error correction for cache memories through adaptive replacement policies
A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.
1. A processor comprising:
a core data cache;
cache control logic to receive:
a hit/miss from the core data cache;
a read/write signal from a load store unit; and
an eviction policy signal indicative of a detectable unrecoverable error failure in time (DUE FIT) rate of the core data cache, the eviction policy signal including one of an aggressive policy value, an intermediate policy value, and a relaxed policy value; and age modification logic to:
modify an age attribute of a modified cache line based on the read/write signal and the eviction policy signal, wherein the age modification logic is to increase the age attribute of modified lines in a way responsive to assertion of the aggressive policy value.
2. The processor of claim 1 , wherein the age modification logic is to increase the age attribute of modified lines responsive to assertion of the intermediate policy value and assertion of the write signal.
3. The processor of claim 1 , further comprising:
DUE FIT estimation logic to estimate the DUE FIT rate.
4. The processor of claim 3 , wherein the DUE FIT estimation logic is to estimate DUE FIT based on a number of modified lines in the core data cache.
5. The processor of claim 1 , wherein the processor includes multiple processing cores and wherein each core includes the cache control logic and the age modification logic to influence eviction policy based on an estimate of the DUE FIT rate for the core.
6. A method, comprising:
obtaining detectable unrecoverable error failure in time (DUE FIT) data indicative of a DUE FIT rate;
comparing the DUE FIT rate to a first threshold; and
responsive to the DUE FIT rate exceeding the first threshold, evicting modified lines stored in a cache memory of a processor preferentially in response to read and write cache miss events, evicting the modified cache lines preferentially in response to cache write miss events responsive to the DUE FIT rate not exceeding the first threshold and exceeding a second threshold, and evicting based on a recency policy in response to cache write miss events when the DUE FIT rate does not exceed the second threshold.
7. The method of claim 6 , wherein responsive to the DUE FIT rate not exceeding the second threshold, setting a relaxed eviction policy wherein lines stored in the cache memory are evicted based on the recency policy in response to the read and write cache miss events.
8. The method of claim 6 , wherein the processor includes a plurality of cores and the method includes performing for each core:
the obtaining of DUE FIT data indicative of a DUE FIT rate;
the comparing of the DUE FIT rate to a first threshold; and
responsive to the DUE FIT rate exceeding the first threshold, the evicting of modified lines stored in the cache memory of the processor preferentially in response to the read and write cache miss events.
9. The method of claim 6 , further comprising, estimating the DUE FIT rate based on an estimate of a number of modified lines stored in the cache memory.
10. A computer system, comprising:
a processor comprising:
a core data cache;
cache control logic to receive:
a hit/miss from the core data cache;
a read/write signal from a load store unit; and
an eviction policy signal indicative of a detectable unrecoverable error failure in time (DUE FIT) rate of the core data cache; and
age modification logic to:
modify an age attribute of a modified cache line based on the read/write signal and the eviction policy signal, to cause the modified cache line to be preferentially evicted in response to a cache miss event when the DUE FIT rate exceeds a first threshold, cause the modified cache line to be preferentially evicted in response to a cache write miss event when the DUE FIT rate is less than the first threshold and exceeds a second threshold, and not modify the age attribute of the modified cache line in response to a cache write miss event when the DUE FIT rate does not exceed the second threshold.
11. The computer system of claim 10 , wherein the eviction policy signal includes an aggressive policy value, an intermediate policy value, and a relaxed policy value.
12. The computer system of claim 11 , wherein the age modification logic is to increase the age attribute of modified lines in a way responsive to assertion of the aggressive policy value.
13. The computer system of claim 11 , wherein the age modification logic is to increase the age attribute of modified lines in a way responsive to assertion of the intermediate policy value and assertion of the write signal.
14. The computer system of claim 10 , further comprising DUE FIT estimation logic to estimate the DUE FIT rate.
15. The computer system of claim 14 , wherein the DUE FIT estimation logic is to estimate the DUE FIT rate based on a number of modified lines in the core data cache.
16. The computer system of claim 10 , wherein the processor includes multiple processing cores and wherein each core includes the cache control logic and the age modification logic to influence eviction policy based on an estimate of the DUE FIT rate for the core.
17. The processor of claim 1 , wherein the age modification logic is to cause the modified cache line to be preferentially evicted in response to a cache miss event when the DUE FIT rate exceeds a first threshold, cause the modified cache line to be preferentially evicted in response to a cache write miss event when the DUE FIT rate is less than the first threshold and exceeds a second threshold, and not modify the age attribute of the modified cache line in response to a cache write miss event when the DUE FIT rate does not exceed the second threshold.