IP Library › Granted Patent US 10,203,878
Granted Patent B2
US 10,203,878 · App. 15/859,372 · Granted Feb 12, 2019

Near memory accelerator

Inventors: Angelo Haller (Brandenburg, DE); Harald Huels (Horb am Neckar, DE); Jan Van Lunteren (Gattikon, CH); Joerg-Stephan Vogt (Holzgerlingen, DE)
Assignee: International Business Machines Corporation
G06F3/0607G06F3/068G06F3/0631G06F3/0659G06F12/023G06F2212/1044
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Quick Facts
Patent No.
US 10,203,878
App. No.
15/859,372
Granted
Feb 12, 2019
Kind
B2
Abstract

A computing system includes a host processor, an access processor having a command port, a near memory accelerator, and a memory unit. The system is adapted to run a software program on the host processor and to offload an acceleration task of the software program to the near memory accelerator. The system is further adapted to provide, via the command port, a first communication path for direct communication between the software program and the near memory accelerator, and to provide, via the command port and the access processor, a second communication path for indirect communication between the software program and the near memory accelerator. A related computer implemented method and a related computer program product are also disclosed.

Claims (14)

1. A computer implemented method for operating a computing system, the computing system comprising a host processor, an access processor having a command port, a near memory accelerator and a memory unit; the method comprising the steps of:

running a software program on the host processor;

offloading an acceleration task of the software program to the near memory accelerator;

providing, via the command port, a first communication path for direct communication between the software program and the near memory accelerator and a second communication path for indirect communication between the software program and the near memory accelerator via the access processor;

writing, by the software program, operand data and/or control data of the acceleration task into the command port; and

reading, by the software program, result data of the acceleration task from the command port.

2. The computer implemented method according to claim 1 , the method further comprising:

reading, by the near memory accelerator, data of the acceleration task directly from the command port; and

writing, by the near memory accelerator, data of the acceleration task directly to the command port.

3. The computer implemented method according to claim 1 , the method further comprising:

reading, by the access processor, data of the acceleration task from the command port;

providing, by the access processor, the data of the acceleration task to the near memory accelerator;

receiving, by the access processor, data of the acceleration task; and

writing, by the access processor, the data of the acceleration task to the command port.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2017
From: HALLER, ANGELO; HUELS, HARALD; VAN LUNTEREN, JAN; VOGT, JOERG-STEPHAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044509/0530 →
Continuity (2)
Continuation 15471372 · Mar 28, 2017
Related Publication 20180284994A1 · Oct 4, 2018
Cited By (2)
US 12,436,679 US 12,475,050