Mixed precision fused multiply-add operator
A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.
1. A method of fused calculation of the sum of an addend and a product of two multiplication operands using a floating-point unit of a proccessor, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent, wherein the multiplication operands are in a lower precision format than the addend, with q>2p, where p is the mantissa size of the multiplication operands precision format and q is the mantissa size of the addend precision format, the method comprising the steps of:
multiplying, using a p-bit multiplier, the mantissas of the multiplication operands;
right-padding the 2p-bit product resulting from the multiplication with zeros to form a q-bit product mantissa;
aligning, with a shifter, the mantissa of the addend and the mantissa of the product based on the exponent values of the addend and multiplication operands; and
adding with an adder, the aligned mantissas of the product and the addend.
2. The method of claim 1 , comprising the steps of:
left-shifting the addend mantissa and the product based on the number of leading zeros in the multiplication operands mantissas; and
decreasing the exponent of the final result by the left-shift amount.
3. A circuit for calculating the fused sum of an addend and a product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent, wherein the multiplication operands are in a lower precision format than the addend, with q>2p, where p is the mantissa size of the multiplication operands precision format and q is the mantissa size of the addend precision format, comprising:
a p-bit multiplier receiving the mantissas of the multiplication operands;
a shift circuit configured to align the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and
an adder configured for processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.
4. The circuit according to claim 3 , comprising:
a zero counter circuit providing the sum of the number of leading zeros of the mantissas of the multiplication operands;
a left-shift circuit connected to act on the output of the multiplier, receiving the output of the zero counter circuit as the shift amount; and
a right-shift circuit connected to act on the mantissa of the addend, receiving as a shift amount a function of the exponents of the addend and multiplication operands, less the output of the zero counter circuit.
5. The circuit according to claim 4 , wherein
the size of the inputs of the adder is 2q bits, plus a few bits for accommodating carry propagation and rounding bits.