Automatic waking of power domains for graphics configuration requests

1. An apparatus comprising:

an interface to receive a graphics configuration request, the graphics configuration request being directed to a target graphics register in a graphics domain, wherein the apparatus is within an interface bridge between a system processor and the graphics domain;

a decouple request processor to process requests including the graphics configuration request, wherein the decouple request processor includes automated handshake logic to provide a handshake with a block controller;

a plurality of registers for storage of data, the plurality of registers including one or more configuration registers that are accessible for storage of the graphics configuration request;

automatic power domain determination logic to identify a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and

wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain;

wherein the block controller is to block the interface bridge to prevent transfer of requests prior to a power domain being in an active power state and to unblock the interface bridge to allow transfer of the configuration request upon determination that the identified power domain is in the active power state.

2. The apparatus of claim 1 , wherein the shared information is derived from a client table including data aligning addresses to clients and power domains for the clients.

3. The apparatus of claim 2 , wherein the information from the client table is shared with message channel routers for a message channel for the graphics domain.

4. The apparatus of claim 1 , wherein the decouple request processor includes an arbiter to select and present configuration requests to active power domains.

5. The apparatus of claim 1 , wherein the one or more configuration registers include one or more decouple request registers.

6. The apparatus of claim 1 , wherein the one or more configuration registers include one or more bits to indicate a completion status for the configuration request.

7. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

receiving a graphics configuration request at one or more configuration registers of an interface bridge, the request being directed to a destination graphics register;

identifying a power domain for the destination graphics register, wherein the identification of the power domain is based at least in part on shared information maintained for address routing and blocking the interface bridge to prevent transfer of requests prior to the power domain being in an active power state;

determining whether the identified power domain is in a reduced power state;

upon determining that the identified power domain is in a reduced power state, generating a wake indication for the identified power domain;

unblocking the interface bridge to allow transfer of the configuration request upon determination that the identified power domain is in the active power state; and

transferring the configuration request to the destination graphics register.

8. The medium of claim 7 , wherein the one or more configuration registers are contained in the interface bridge between a processor and a graphics domain.

9. The medium of claim 8 , wherein the configuration request is received from a driver run by a processor.

10. The medium of claim 7 , wherein the shared information includes data aligning addresses to clients and power domains for the clients.

11. The medium of claim 7 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:

setting a completion status bit of the one or more configuration registers upon receiving the configuration request and clearing the completion status bit upon transferring the configuration request to the destination graphics register.

12. The medium of claim 7 , wherein the one or more configuration registers include one or more decouple request registers.

13. The medium of claim 7 , wherein transferring the configuration request to the destination graphics register includes arbitrating to select and present configuration requests to active power domains.

14. A system comprising:

a processor to process data;

a graphics domain for graphics operation;

a driver run by the processor to provide configuration requests to target graphics registers in the graphics domain; and

an interface bridge between the processor and the graphics domain, the interface bridge including:

a plurality of configuration registers, the configuration registers including a plurality of registers to receive graphics configuration requests,

an automatic power domain mechanism to identify a power domain for a target graphics register for each configuration request received from the driver, to determine whether an identified power domain is in a reduced power state, and, upon determining that an identified power domain is in a reduced power state, to generate a wake indicate for the power domain, and

a processor to process configuration requests, wherein the processor to process configuration requests is a decouple request processor;

wherein the automatic power domain mechanism is to identify a power domain for the target graphics register based on shared information accessed by the automatic power domain mechanism; and

wherein the decouple request processor includes automated handshake logic to provide a handshake with a block controller, the block controller to block the interface bridge to prevent transfer of requests prior to a power domain being in an active power state and to unblock the interface bridge to allow transfer of the configuration request upon determination that the identified power domain is in the active power state.

15. The system of claim 14 , wherein the shared information includes information derived from a client table including data aligning addresses to clients and power domains for the clients.

16. The system of claim 14 , wherein the interface bridge is powered on during operation of the system.

17. The system of claim 14 , wherein the decouple request processor includes an arbiter to select and present configuration requests to active power domains.