Implicit fence for write messages
Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
1. A graphics processor comprising:
a first cache;
a graphics core associated with the first cache, the graphics core including a processing resource and a surface state cache; and
memory access circuitry to process a memory access message received from the processing resource, the memory access circuitry including fence circuitry to order memory operations according to a fence instruction, wherein the memory access circuitry is configured to:
receive a write request message in response to execution of an instruction by the processing resource to perform a write to a memory surface;
determine a scope attribute and cache attributes associated with the write request message including to determine a first cache attribute based on a request descriptor associated with the write request message and determine a second cache attribute based on state information associated with the memory surface within the surface state cache;
perform a memory store operation according to the scope attribute and the cache attributes;
examine a request descriptor of the write request message for presence of an implicit fence attribute; and
request a fence operation via the fence circuitry in response to detection of the implicit fence attribute within the request descriptor, the fence operation to order a write sequence to the memory surface.
2. The graphics processor of claim 1 , wherein the memory access circuitry is configured to arbitrate between the first cache attribute and the second cache attribute according to respective priorities associated with the first cache attribute and the second cache attribute.
3. The graphics processor of claim 2 , the first cache attribute and the second cache attribute to indicate whether data of the memory surface is cacheable in the first cache.
4. The graphics processor of claim 3 , wherein the second cache attribute is to specify a default cache attribute and the first cache attribute is to specify an override of the default cache attribute.
5. The graphics processor of claim 4 , wherein the second cache attribute is to indicate to cache data of the memory surface in the first cache and a second cache and the first cache attribute indicates to bypass the first cache and write to a second cache.
6. The graphics processor of claim 5 , wherein the memory access circuitry is configured to:
invalidate a cache line within the first cache that maps to an address associated with the write to the memory surface; and
cache data associated with the write to the memory surface in the second cache.
7. The graphics processor of claim 1 , wherein the graphics core includes a surface state cache and the memory access circuitry is to determine the scope attribute via state information within the surface state cache.
8. The graphics processor of claim 7 , wherein the scope attribute is to indicate visibility of a memory allocation associated with the memory surface and the scope attribute is selected from a set of attributes including a private scope, a local scope, and a global scope.
9. The graphics processor of claim 8 , wherein data having a private scope is visible to a single thread, data having a local scope is visible within the graphics core, and data having the global scope is visible within the graphics core and outside of the graphics core.
10. A method comprising:
receiving, at memory access circuitry of a graphics core within a graphics processor, a write request message in response to execution of an instruction by a processing resource of the graphics core, the write request message requesting a write to a memory surface in memory of the graphics processor;
determining a scope attribute and cache attributes associated with the write request message via state information within a surface state cache of the graphics core, wherein the scope attribute indicates visibility of a memory allocation associated with the memory surface and is selected from a set of attributes including a private scope, a local scope, and a global scope;
performing a memory store operation according to the scope attribute and the cache attributes;
examining a request descriptor of the write request message for presence of an implicit fence attribute; and
requesting a fence operation via fence circuitry within the memory access circuitry in response to detection of the implicit fence attribute within the request descriptor, the fence operation to order a write sequence to the memory surface.
11. The method of claim 10 , wherein data having a private scope is visible to a single thread, data having a local scope is visible within the graphics core, and data having the global scope is visible within the graphics core and outside of the graphics core.
12. The method of claim 10 , wherein determining the cache attributes associated with write request message includes:
determining a first cache attribute based on a request descriptor associated with the write request message; and
determining a second cache attribute based on state information associated with the memory surface, the state information stored in the surface state cache.
13. The method of claim 12 further comprising arbitrating between the first cache attribute and the second cache attribute according to respective priorities associated with the first cache attribute and the second cache attribute.
14. A graphics processing system comprising:
a memory device configured to store instructions; and
a graphics processor coupled with the memory device, the graphics processor comprising:
a first cache coupled with the memory device;
a graphics core coupled with the memory device and associated with the first cache, the graphics core including a processing resource and a surface state cache; and
memory access circuitry to process a memory access message received from the processing resource, the memory access circuitry including fence circuitry to order memory operations according to a fence instruction, wherein the memory access circuitry is configured to:
receive a write request message in response to execution of an instruction by the processing resource to perform a write to a memory surface;
determine a scope attribute and cache attributes associated with the write request message including to determine a first cache attribute based on a request descriptor associated with the write request message and determine a second cache attribute based on state information associated with the memory surface within the surface state cache;
perform a memory store operation according to the scope attribute and the cache attributes;
examine a request descriptor of the write request message for presence of an implicit fence attribute; and
request a fence operation via the fence circuitry in response to detection of the implicit fence attribute within the request descriptor, the fence operation to order a write sequence to the memory surface.
15. The graphics processing system of claim 14 , wherein the scope attribute is to indicate visibility of a memory allocation associated with the memory surface and the scope attribute is selected from a set of attributes including a private scope, a local scope, and a global scope.
16. The graphics processing system of claim 15 , wherein data having a private scope is visible to a single thread, data having a local scope is visible within the graphics core, and data having the global scope is visible within the graphics core and outside of the graphics core.
17. The graphics processing system of claim 14 wherein the memory access circuitry is configured to arbitrate between the first cache attribute and the second cache attribute according to respective priorities associated with the first cache attribute and the second cache attribute.
18. The graphics processing system of claim 17 , the first cache attribute and the second cache attribute to indicate whether data of the memory surface is cacheable in the first cache.
19. The graphics processing system of claim 18 , wherein the second cache attribute is to specify a default cache attribute and the first cache attribute is to specify an override of the default cache attribute.
20. The graphics processing system of claim 19 , wherein the second cache attribute is to indicate to cache data of the memory surface in the first cache and a second cache and the first cache attribute indicates to bypass the first cache and write to a second cache.